Intel® Quartus® Prime Pro Edition User Guide: Design Compilation

ID 683236
Date 1/27/2022
Public

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2.3.1. Running Synthesis

Run design synthesis as part of a full compilation, or as an independent process. Before running synthesis, specify settings that control synthesis processing. The Messages window dynamically displays processing information, warnings, or errors. Following Analysis & Synthesis processing, the Synthesis report provides detailed information about the synthesis of your project. To run synthesis, perform the following steps.
  1. Create or open an Intel® Quartus® Prime project with valid design files for compilation.
  2. Before running synthesis, specify any of the following settings and constraints that impact synthesis:
    • To specify options for the synthesis of Verilog HDL input files, click Assignments > Settings > Verilog HDL Input.
    • To specify options for the synthesis of VHDL input files, click Assignments > Settings > VHDL Input.
    • To specify options that affect compilation processing time, click Assignments > Settings > Compilation Process Settings.
    • To specify the Compiler's high-level optimization strategy and other options, click Assignments > Settings > Compiler Settings. Specify the optimization goal, according to Compiler Optimization Modes.
    • On the Compiler Settings page enable or disable the Enable Intermediate Fitter Snapshots option to preserve snapshots for the Plan, Place, Route, and Retime stages any time you run full compilation. The Compiler does not generate intermediate snapshots by default.
    • To specify advanced synthesis settings, click Assignments > Settings > Compiler Settings, and then click Advanced Settings (Synthesis).
    • Consider enabling fractal synthesis for arithmetic-intensive designs that exhaust all DSP resources, according to the guidelines in Fractal Synthesis Optimization.
  3. To run synthesis, click Synthesis on the Compilation Dashboard.