Stratix® 10 Hard Processor System Technical Reference Manual
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24.2. Watchdog Timers Block Diagram and System Integration
Each watchdog timer consists of a slave interface for control and status register (CSR) access, a register block, and a 32-bit down counter that operates on the slave interface clock (l4_sys_free_clk). A pause input, driven by the system manager, optionally pauses the counter when a CPU is being debugged.
The watchdog timer drives an interrupt request to the MPU and a reset request to the reset manager.