FIR II IP Intel® FPGA IP: User Guide

ID 683208
Date 9/17/2024
Public
Document Table of Contents

4.4.3. Channel Input and Output Format

The FIR II IP requires the inputs and the outputs to be in the same format when the number of input channels is more than one. The input data to the IP must be arranged horizontally according to the channels and vertically according to the wires. The outputs should then come out in the same order, counting along horizontal row first, vertical column second.