1. Stratix® 10 Clocking and PLL Overview
2. Stratix® 10 Clocking and PLL Architecture and Features
3. Stratix® 10 Clocking and PLL Design Considerations
4. Stratix® 10 Clocking and PLL Implementation Guides
5. Clock Control Intel® FPGA IP Core References
6. IOPLL Intel® FPGA IP Core References
7. IOPLL Reconfig Intel® FPGA IP Core References
8. Stratix® 10 Clocking and PLL User Guide Archives
9. Document Revision History for the Stratix® 10 Clocking and PLL User Guide
2.2.1. PLL Features
2.2.2. PLL Usage
2.2.3. PLL Architecture
2.2.4. PLL Control Signals
2.2.5. Clock Feedback Modes
2.2.6. Clock Multiplication and Division
2.2.7. Programmable Phase Shift
2.2.8. Programmable Duty Cycle
2.2.9. PLL Cascading
2.2.10. Clock Switchover
2.2.11. PLL Reconfiguration and Dynamic Phase Shift
2.2.12. PLL Calibration
4.3.4.1. Design Example 1: .mif Streaming Reconfiguration Using IOPLL Reconfig IP Core
4.3.4.2. Design Example 2: Advanced Mode Reconfiguration Using IOPLL Reconfig IP Core
4.3.4.3. Design Example 3: Clock Gating Reconfiguration Using IOPLL Reconfig IP Core
4.3.4.4. Design Example 4: Dynamic Phase Shift Using IOPLL Reconfig IP Core
2.1.3.1. Dedicated Clock Input Pins
The sources of dedicated clock input pins are as follows:
- fPLL—REFCLK_GXB[L,R][1,4][C,D,E,F,G,H,I,J,K,L,M,N]_CH[B,T][p,n] from transceiver column
- I/O PLL—CLK_[2,3][A..N]_[0,1][p,n] from I/O column
You can use the dedicated clock input pins for high fan-out control signals, such as asynchronous clears, presets, and clock enables, for protocol signals through the programmable clock routing.
The dedicated clock input pins for an I/O PLL can be either differential clocks or single-ended clocks. The dedicated clock input pins for fPLL only support differential clocks and do not support single-ended clocks.
Driving a PLL over programmable clock routing can cause higher jitter at the PLL input, and the PLL is not able to fully compensate for the programmable clock routing. Intel recommends using the dedicated clock input pins for optimal performance to drive the PLLs.