Quartus® Prime Pro Edition User Guide: Design Constraints

Download PDF
ID 683143
Date 8/07/2024
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
Answers to Top FAQs 1. Constraining Designs 2. Interface Planning 3. Managing Device I/O Pins 4. Quartus® Prime Pro Edition User Guide: Design Constraints Document Archives A. Quartus® Prime Pro Edition User Guides
1. Constraining Designs x
1.1. Specifying Design Constraints in the GUI 1.2. Constraining Designs with Tcl Scripts 1.3. A Fully Iterative Scripted Flow 1.4. Constraining Designs Revision History
1.1. Specifying Design Constraints in the GUI x
1.1.1. Global Constraints and Assignments 1.1.2. Node, Entity, and Instance-Level Constraints 1.1.3. Probing Between Components of the Quartus® Prime GUI 1.1.4. Specifying Timing Constraints
1.1.2. Node, Entity, and Instance-Level Constraints x
1.1.2.1. Specify Instance-Specific Constraints in Assignment Editor 1.1.2.2. Specify NoC Constraints in NoC Assignment Editor 1.1.2.3. Specify Dual Simplex Assignments in DS Assignment Editor 1.1.2.4. Specify I/O Constraints in Pin Planner 1.1.2.5. Plan Interface Constraints in Interface Planner and Tile Interface Planner 1.1.2.6. Adjust Constraints with the Chip Planner 1.1.2.7. Constraining Designs with the Design Partition Planner
1.1.2.1. Specify Instance-Specific Constraints in Assignment Editor x
1.1.2.1.1. Specifying Multi-Dimensional Bus Constraints
1.1.2.2. Specify NoC Constraints in NoC Assignment Editor x
1.1.2.2.1. NoC Assignment Editor Interface Controls 1.1.2.2.2. Troubleshooting NoC Assignment Editor
1.2. Constraining Designs with Tcl Scripts x
1.2.1. Create a Project and Apply Constraints 1.2.2. Assigning a Pin 1.2.3. Generating Quartus® Prime Settings Files 1.2.4. Synopsys* Design Constraint (.sdc) Files 1.2.5. Tcl-only Script Flows
2. Interface Planning x
2.1. Using Interface Planner 2.2. Using Tile Interface Planner 2.3. Interface Planning Revision History
2.1. Using Interface Planner x
2.1.1. Interface Planner User Interface 2.1.2. Interface Planner General Tool Flow 2.1.3. Interface Planner NoC Tool Flow 2.1.4. Interface Planner Reports
2.1.1. Interface Planner User Interface x
2.1.1.1. Flow Controls 2.1.1.2. Home Tab Controls 2.1.1.3. Assignments Tab Controls 2.1.1.4. Plan Tab Controls 2.1.1.5. Reports Tab Controls
2.1.2. Interface Planner General Tool Flow x
2.1.2.1. Step 1: Setup and Synthesize the Project 2.1.2.2. Step 2: Initialize Interface Planner 2.1.2.3. Step 3: Update Plan with Project Assignments 2.1.2.4. Step 4: Plan Periphery Placement 2.1.2.5. Step 5: Report Placement Data 2.1.2.6. Step 6: Validate and Export Plan Constraints
2.1.2.4. Step 4: Plan Periphery Placement x
2.1.2.4.1. Plan Clock Networks 2.1.2.4.2. Saving & Loading Floorplans
2.1.4. Interface Planner Reports x
2.1.4.1. Report Summary 2.1.4.2. Report Pins 2.1.4.3. Report HSSI Channels 2.1.4.4. Report Clocks 2.1.4.5. Report Periphery Locations 2.1.4.6. Report Cell Connectivity 2.1.4.7. Report Instance Assignments 2.1.4.8. Report NoC Performance
2.2. Using Tile Interface Planner x
2.2.1. Tile Interface Planner Terminology 2.2.2. Tile Interface Planner Tool Flow 2.2.3. Constraining Dynamic Reconfiguration IP 2.2.4. Tile Interface Planner GUI Reference
2.2.2. Tile Interface Planner Tool Flow x
2.2.2.1. Step 1: Instantiate IP and Run Design Analysis 2.2.2.2. Step 2: Initialize Tile Interface Planner 2.2.2.3. Step 3: Update Plan with Project Assignments 2.2.2.4. Step 4: Create a Tile Plan 2.2.2.5. Step 5: Save Tile Plan Assignments 2.2.2.6. Step 6: Run Logic Generation and Design Synthesis
2.2.2.4. Step 4: Create a Tile Plan x
2.2.2.4.1. Placing IP Components 2.2.2.4.2. Constraining IP Building Blocks
2.2.3. Constraining Dynamic Reconfiguration IP x
2.2.3.1. Defining a Dynamic Reconfiguration Group 2.2.3.2. Assigning Dynamic Reconfiguration Group Placement
2.2.4. Tile Interface Planner GUI Reference x
2.2.4.1. Flow Controls 2.2.4.2. Home Tab 2.2.4.3. Assignments Tab Controls 2.2.4.4. Plan Tab Controls 2.2.4.5. Tcl Console Window
2.2.4.4. Plan Tab Controls x
2.2.4.4.1. Design Tree and Filters 2.2.4.4.2. Reconfiguration Groups View 2.2.4.4.3. Legal Locations Pane
3. Managing Device I/O Pins x
3.1. I/O Planning Overview 3.2. Assigning I/O Pins 3.3. Importing and Exporting I/O Pin Assignments 3.4. Validating Pin Assignments 3.5. Verifying I/O Timing 3.6. Viewing Routing and Timing Delays 3.7. Scripting API 3.8. Managing Device I/O Pins Revision History
3.1. I/O Planning Overview x
3.1.1. Basic I/O Planning Flow 3.1.2. Integrating PCB Design Tools 3.1.3. Intel FPGA Device and I/O Terminology
3.2. Assigning I/O Pins x
3.2.1. Assigning to Exclusive Pin Groups 3.2.2. Assigning Slew Rate and Drive Strength 3.2.3. Assigning I/O Banks 3.2.4. Changing Pin Planner Highlight Colors 3.2.5. Showing I/O Lanes 3.2.6. Assigning Differential Pins 3.2.7. Entering Pin Assignments with Tcl Commands 3.2.8. Entering Pin Assignments in HDL Code
3.2.6. Assigning Differential Pins x
3.2.6.1. Overriding I/O Placement Rules on Differential Pins
3.2.8. Entering Pin Assignments in HDL Code x
3.2.8.1. Using Low-Level I/O Primitives
3.3. Importing and Exporting I/O Pin Assignments x
3.3.1. Importing and Exporting for PCB Tools 3.3.2. Migrating Assignments to Another Target Device
3.4. Validating Pin Assignments x
3.4.1. I/O Assignment Validation Rules 3.4.2. I/O Assignment Analysis 3.4.3. Understanding I/O Analysis Reports
3.4.2. I/O Assignment Analysis x
3.4.2.1. Early I/O Assignment Analysis Without Design Files 3.4.2.2. I/O Assignment Analysis With Design Files 3.4.2.3. Overriding Default I/O Pin Analysis
3.5. Verifying I/O Timing x
3.5.1. Running Advanced I/O Timing 3.5.2. Adjusting I/O Timing and Power with Capacitive Loading
3.5.1. Running Advanced I/O Timing x
3.5.1.1. Board Trace Models 3.5.1.2. Defining the Board Trace Model 3.5.1.3. Modifying the Board Trace Model 3.5.1.4. Specifying Near-End vs Far-End I/O Timing Analysis 3.5.1.5. Advanced I/O Timing Analysis Reports
3.7. Scripting API x
3.7.1. Generate Mapped Netlist 3.7.2. Reserve Pins 3.7.3. Set Location 3.7.4. Exclusive I/O Group 3.7.5. Slew Rate and Current Strength
Answers to Top FAQs
1. Constraining Designs
2. Interface Planning
3. Managing Device I/O Pins
4. Quartus® Prime Pro Edition User Guide: Design Constraints Document Archives
A. Quartus® Prime Pro Edition User Guides

2.3. Interface Planning Revision History

This document has the following revision history:
Table 26.  Interface Planning Revision History
Document Version Intel Quartus Prime Version Changes
2024.08.07 24.1
  • Replaced steps with link in Interface Planner NoC Tool Flow topic.
2024.04.01 24.1
  • Applied initial Altera rebranding throughout.
2023.10.02 23.3
  • Updated screenshot in Step 1: Instantiate IP and Run Design Analysis for latest Compilation Dashboard.
2023.04.03 23.1
  • Added new Interface Planner NoC Tool Flow section describing general use of new Interface Planner features that support the Hard Memory NoC in Agilex® 7 M-Series FPGAs.
  • Added new Report NoC Performance topic describing the new NoC Performance Report that Interface Planner can generate.
  • Updated product family name to "Intel Agilex 7."
2022.09.26 22.3
  • Updated Defining a Dynamic Reconfiguration Group topic to describe automated placement of children and siblings in DR groups.
  • Added note and image to Assigning Dynamic Reconfiguration Group Placement topic to describe automated placement of children and siblings in DR groups.
2022.06.21 22.2
  • Updated Constraining Dynamic Reconfiguration Group IP topic for Tile Assignment Editor support.
  • Added new Defining a Dynamic Reconfiguration Group topic describing use of new Tile Assignment Editor.
  • Updated Assigning Dynamic Reconfiguration Group Placement topic for support of interactive placement in Tile Interface Planner.
2022.03.28 22.1
  • Added dynamic reconfiguration to Tile Interface Planner Terminology topic.
  • Retitled and updated Dynamic Reconfiguration Multi-Rate IP Tile Planning topic for new display of base and secondary dynamic reconfiguration profiles.
  • Added new Reconfiguration Groups View topic.
2021.10.04 21.3
  • Updated Tile Interface Planner Terminology JSON file and IP building block definitions.
  • Updated GUI options in Step 3: Update Plan Assignments and Assignments Tab Controls topics.
  • Added "Multi-Rate IP Tile Planning" topic.
  • Updated "Step 5: Save Tile Plan Assignments" for latest GUI.
  • Added new video demo link to Interface Planning topic.
  • Added new controls to Flow Controls topic.
  • Revised Plan Tab Controls topic for new toolbar controls.
  • Added application note link to Step 3: Update Plan with Project Assignments
2021.06.21 21.2
  • Integrated new Tile Interface Planning section.
2019.04.01 19.1.0
  • Updated "Plan Tab Controls" to describe new color coding controls for I/O banks, differential pin pairs, DQ/DQS pins, and PCIe hard IP pins.
  • Update screenshots and procedure steps for latest user interface.
2018.05.07 18.0.0
  • Initial release in Design Constraints User Guide: Intel Quartus Prime Pro Edition.
  • Updated Step 2: Initialize Interface Planner to remove the requirement to close Intel Quartus Prime.
  • Updated Step 4: Plan Periphery Placement to describe when the Locate Node command is disabled.
2017.11.06 17.1.0
  • Removed support for the Clocking feature for Intel Stratix 10. Intel Stratix 10 clocks must use Autoplace Selected.
  • Renamed BluePrint to Interface Planner.
  • Renamed chapter from BluePrint Design Planning to Interface Planning.
2016.10.31 16.1.0
  • Implemented Intel rebranding.
2016.05.03 16.0.0
  • Added Plan Clock Networks topic.
  • Added Saving and Loading Floorplans topic.
  • Added Undo/Redo command descriptions.
  • Added Flow control description.
  • Added note about panning feature.
  • Updated all screenshots for latest GUI.
2015.11.02 15.1.0
  • Changed instances of Quartus II to Quartus Prime.
  • Integration of content into Quartus Prime Handbook.
  • Added descriptions of new dynamic reports.
  • Added Package View description.
  • Added GUI controls reference.
2015.05.04 15.0.0 Second beta release of document on Molson. Added information about the following subjects:
  • Overview information
  • Reset Plan command
  • Legal Assignments list and prompt
  • Tcl console
2014.12.15 14.1. First beta release of document on Molson.
Level Two Title