Intel Agilex® 7 SEU Mitigation User Guide

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ID 683128
Date 2/20/2024
Public
Document Table of Contents
Document Table of Contents x
1. Intel Agilex® 7 SEU Mitigation Overview 2. Intel Agilex® 7 CRAM Error Mitigation 3. Secure Device Manager ECC and SmartVID Errors Detection 4. Intel Agilex® 7 SEU Mitigation Implementation Guides 5. IP and Software References 6. Intel Agilex® 7 SEU Mitigation User Guide Archives 7. Document Revision History for the Intel Agilex® 7 SEU Mitigation User Guide
1. Intel Agilex® 7 SEU Mitigation Overview x
1.1. SEU Mitigation Techniques 1.2. Configuration RAM 1.3. Memory Blocks 1.4. Secure Device Manager ECC and SmartVID 1.5. Triple Modular Redundancy 1.6. Failure Rates
2. Intel Agilex® 7 CRAM Error Mitigation x
2.1. CRAM Error Detection and Correction 2.2. Error Message Queue 2.3. Scrubbing 2.4. SEU Sensitivity Processing 2.5. Design Hierarchy Sensitivity Classification 2.6. Evaluation of System Response to Upsets
2.3. Scrubbing x
2.3.1. Internal Scrubbing 2.3.2. Priority Scrubbing
2.4. SEU Sensitivity Processing x
2.4.1. Advanced SEU Detection Intel® FPGA IP
2.4.1. Advanced SEU Detection Intel® FPGA IP x
2.4.1.1. Release Information for Advanced SEU Detection Intel® FPGA IP 2.4.1.2. On-Chip Lookup Sensitivity Processing 2.4.1.3. Off-Chip Lookup Sensitivity Processing 2.4.1.4. Sensitivity Map Header Lookup
2.5. Design Hierarchy Sensitivity Classification x
2.5.1. Hierarchy Tagging
2.6. Evaluation of System Response to Upsets x
2.6.1. Fault Injection Debugger
3. Secure Device Manager ECC and SmartVID Errors Detection x
3.1. SDM ECC Error Message Bits 3.2. SmartVID Error Message Bits 3.3. SDM ECC and SmartVID Errors Signals Behavior
4. Intel Agilex® 7 SEU Mitigation Implementation Guides x
4.1. Setting the SEU_ERROR Pin 4.2. Setting Up the SEU Mitigation Features 4.3. Enabling Priority Scrubbing 4.4. Assigning Regions for Hierarchy Tagging 4.5. Sensitivity Map Header 4.6. Using the Fault Injection Debugger
4.5. Sensitivity Map Header x
4.5.1. Programming the .smh File into Memory 4.5.2. Looking up the Sensitivity Map Header
4.5.2. Looking up the Sensitivity Map Header x
4.5.2.1. Sensitivity Map Header Revision 4 File Format Reference
4.6. Using the Fault Injection Debugger x
4.6.1. Launching and Setting Up the Fault Injection Debugger 4.6.2. Configuring Your Device using a Software Object File (.sof) 4.6.3. Constraining Regions for Fault Injection 4.6.4. Injecting Errors to Random Locations 4.6.5. Injecting Errors to Specific Locations 4.6.6. Injecting Double Adjacent Errors 4.6.7. Injecting SDM ECC Errors 4.6.8. Analyzing SEU or SDM ECC Errors Using Signal Tap
4.6.6. Injecting Double Adjacent Errors x
4.6.6.1. Injecting Double Adjacent Errors: Command-Line Interface 4.6.6.2. Injecting Double Adjacent Errors: GUI with Tcl Console
4.6.7. Injecting SDM ECC Errors x
4.6.7.1. Injecting SDM ECC Errors: Command-Line Interface 4.6.7.2. Injecting SDM ECC Errors: GUI
5. IP and Software References x
5.1. Advanced SEU Detection Intel® FPGA IP References 5.2. Fault Injection Debugger Software References
5.1. Advanced SEU Detection Intel® FPGA IP References x
5.1.1. Advanced SEU Detection Intel® FPGA IP Parameter Settings 5.1.2. Advanced SEU Detection Intel® FPGA IP Ports
5.2. Fault Injection Debugger Software References x
5.2.1. Fault Injection Debugger GUI Tool 5.2.2. Fault Injection Debugger Command-Line Interface
1. Intel Agilex® 7 SEU Mitigation Overview
2. Intel Agilex® 7 CRAM Error Mitigation
3. Secure Device Manager ECC and SmartVID Errors Detection
4. Intel Agilex® 7 SEU Mitigation Implementation Guides
5. IP and Software References
6. Intel Agilex® 7 SEU Mitigation User Guide Archives
7. Document Revision History for the Intel Agilex® 7 SEU Mitigation User Guide

4.5.1. Programming the .smh File into Memory

You can program the .smh into any type of memory. The following example procedure generates the programming file for quad serial peripheral interface (SPI) flash memory.
  1. Rename the .smh to <file_name>.hex. If required, convert the file to a little-endian .hex file.
  2. From the Intel® Quartus® Prime menu, select File > Programming File Generator.
  3. In the Device family box, select Agilex 7.
  4. In the Configuration mode box, select Active Serial x4.
    Figure 11. Programming File Generator Window


  5. In the Output Files tab:
    1. Specify the Output directory and Name for the output file.
      Note: The output directory you specify must already exist in the file system.
    2. Select JTAG Indirect Configuration File (.jic).
    3. Select Memory Map File (.map),
  6. In the Input Files tab:
    1. Click Add Raw Data.
    2. Navigate your file system and select the .hex file and click Open.
    3. Click to select the file in the list and then click Properties.
    4. In the Input File Properties window, if you want to use the Intel® Quartus® Prime Programmer to configure your device, select On in the Bit swap box and click OK.
      Note: Turning on Bitswap generates little-endian programming files, as required by the Intel® Quartus® Prime Programmer. If you use a different programming tool, you can keep Bitswap off, as required by your tool.
  7. In the Configuration Device tab:
    1. Click Add Device.
    2. In the Configuration Device window, click to select your configuration device and click OK.
    3. Click to select the configuration device in the list and then click Add Partition.
    4. In the Add Partition windows, select the file in the Input file box, select Start in the Address Mode box, and then click OK.
    5. Click Select.
    6. In the Select Devices window, click Agilex 7 in the Device family list, select your flash loader device in the Device name list, and then click OK.
  8. Click Generate.
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