Quartus® Prime Pro Edition User Guide: Third-party Synthesis

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ID 683122
Date 5/23/2025
Public
Document Table of Contents
Document Table of Contents x
Answers to Top FAQs 1. Siemens EDA Precision* RTL Synthesis Support 2. Synopsys Synplify* Support A. Quartus® Prime Pro Edition User Guides
1. Siemens EDA Precision* RTL Synthesis Support x
1.1. About Precision RTL Synthesis Support 1.2. Precision RTL Integration Flow 1.3. Altera Device Family Support 1.4. Precision RTL Generated Files 1.5. Creating and Compiling a Project in the Precision Synthesis Software 1.6. Mapping the Design with Precision RTL 1.7. Synthesizing the Design and Evaluating the Results 1.8. Guidelines for Altera IP Cores and Architecture-Specific Features 1.9. Siemens EDA Precision* RTL Synthesis Support Revision History
1.2. Precision RTL Integration Flow x
1.2.1. Timing Optimization
1.6. Mapping the Design with Precision RTL x
1.6.1. Setting Timing Constraints 1.6.2. Setting Mapping Constraints 1.6.3. Assigning Pin Numbers and I/O Settings 1.6.4. Assigning I/O Registers 1.6.5. Disabling I/O Pad Insertion 1.6.6. Controlling Fan-Out on Data Nets
1.6.5. Disabling I/O Pad Insertion x
1.6.5.1. Preventing the Precision RTL Software from Adding I/O Pads 1.6.5.2. Preventing the Precision RTL Software from Adding an I/O Pad on an Individual Pin
1.7. Synthesizing the Design and Evaluating the Results x
1.7.1. Obtaining Accurate Logic Utilization and Timing Analysis Reports
1.8. Guidelines for Altera IP Cores and Architecture-Specific Features x
1.8.1. Instantiating IP Cores With IP Catalog-Generated Verilog HDL Files 1.8.2. Instantiating IP Cores With IP Catalog-Generated VHDL Files 1.8.3. Instantiating Intellectual Property With the IP Catalog and Parameter Editor 1.8.4. Instantiating Black Box IP Functions With Generated Verilog HDL Files 1.8.5. Instantiating Black Box IP Functions With Generated VHDL Files 1.8.6. Inferring Altera IP Cores from HDL Code
1.8.6. Inferring Altera IP Cores from HDL Code x
1.8.6.1. Multipliers 1.8.6.2. Setting the Use Dedicated Multiplier Option 1.8.6.3. Setting the dedicated_mult Attribute 1.8.6.4. Inferring Multiplier-Accumulators and Multiplier-Adders 1.8.6.5. Controlling DSP Block Inference 1.8.6.6. Inferring RAM and ROM
1.8.6.1. Multipliers x
1.8.6.1.1. Controlling DSP Block Inference for Multipliers
2. Synopsys Synplify* Support x
2.1. About Synplify Support 2.2. Synplify Software Integration Flow 2.3. Hardware Description Language Support 2.4. Altera Device Family Support 2.5. Tool Setup 2.6. Synplify Software Generated Files 2.7. Design Constraints Support 2.8. Simulation and Formal Verification 2.9. Synplify Optimization Strategies 2.10. Guidelines for Altera IP Cores and Architecture-Specific Features 2.11. Synopsys Synplify* Support Revision History 2.12. Quartus Prime Pro Edition User Guide: Third-Party Synthesis Archives
2.5. Tool Setup x
2.5.1. Specifying the Quartus® Prime Software Version
2.7. Design Constraints Support x
2.7.1. Running the Quartus® Prime Software Manually With the Synplify-Generated Tcl Script 2.7.2. Passing Timing Analyzer SDC Timing Constraints to the Quartus® Prime Software
2.7.2. Passing Timing Analyzer SDC Timing Constraints to the Quartus® Prime Software x
2.7.2.1. Individual Clocks and Frequencies 2.7.2.2. Input and Output Delay 2.7.2.3. Multicycle Path 2.7.2.4. False Path
2.9. Synplify Optimization Strategies x
2.9.1. Using Synplify Premier to Optimize Your Design 2.9.2. Using Implementations in Synplify Pro or Premier 2.9.3. Timing-Driven Synthesis Settings 2.9.4. FSM Compiler 2.9.5. Optimization Attributes and Options 2.9.6. Altera-Specific Attributes
2.9.3. Timing-Driven Synthesis Settings x
2.9.3.1. Clock Frequencies 2.9.3.2. Multiple Clock Domains 2.9.3.3. Input and Output Delays 2.9.3.4. Multicycle Paths 2.9.3.5. False Paths
2.9.4. FSM Compiler x
2.9.4.1. FSM Explorer in Synplify Pro and Premier
2.9.5. Optimization Attributes and Options x
2.9.5.1. Retiming in Synplify Pro and Premier 2.9.5.2. Maximum Fan-Out 2.9.5.3. Preserving Nets 2.9.5.4. Register Packing 2.9.5.5. Resource Sharing 2.9.5.6. Preserving Hierarchy 2.9.5.7. Register Input and Output Delays 2.9.5.8. syn_direct_enable 2.9.5.9. I/O Standard
2.9.6. Altera-Specific Attributes x
2.9.6.1. altera_chip_pin_lc 2.9.6.2. altera_io_powerup 2.9.6.3. altera_io_opendrain
2.10. Guidelines for Altera IP Cores and Architecture-Specific Features x
2.10.1. Instantiating Altera IP Cores with the IP Catalog 2.10.2. Including Files for Quartus® Prime Placement and Routing Only 2.10.3. Inferring Altera IP Cores from HDL Code
2.10.1. Instantiating Altera IP Cores with the IP Catalog x
2.10.1.1. Instantiating Altera IP Cores with IP Catalog Generated Verilog HDL Files 2.10.1.2. Instantiating Altera IP Cores with IP Catalog Generated VHDL Files 2.10.1.3. Changing Synplify’s Default Behavior for Instantiated Altera IP Cores 2.10.1.4. Instantiating Intellectual Property with the IP Catalog and Parameter Editor 2.10.1.5. Instantiating Black Box IP Cores with Generated Verilog HDL Files 2.10.1.6. Instantiating Black Box IP Cores with Generated VHDL Files 2.10.1.7. Other Synplify Software Attributes for Creating Black Boxes
2.10.3. Inferring Altera IP Cores from HDL Code x
2.10.3.1. Inferring Multipliers 2.10.3.2. Inferring RAM 2.10.3.3. RAM Initialization 2.10.3.4. Inferring ROM 2.10.3.5. Inferring Shift Registers
2.10.3.1. Inferring Multipliers x
2.10.3.1.1. Resource Balancing 2.10.3.1.2. Controlling the DSP Block Inference 2.10.3.1.3. Signal Level Attribute
Answers to Top FAQs
1. Siemens EDA Precision* RTL Synthesis Support
2. Synopsys Synplify* Support
A. Quartus® Prime Pro Edition User Guides

1.8.3. Instantiating Intellectual Property With the IP Catalog and Parameter Editor

Many Altera IP functions include a resource and timing estimation netlist that the Precision RTL software can use to synthesize and optimize logic around the IP efficiently. As a result, the Precision RTL software provides better timing correlation, area estimates, and Quality of Results (QoR) than a black box approach.

To create this netlist file, perform the following steps:

  1. Select the IP function in the IP Catalog.
  2. Click Next to open the Parameter Editor.
  3. Click Set Up Simulation, which sets up all the EDA options.
  4. Turn on the Generate netlist option to generate a netlist for resource and timing estimation and click OK.
  5. Click Generate to generate the netlist file.

The Quartus® Prime software generates a file <output file>_syn.v. This netlist contains the “gray box” information for resource and timing estimation, but does not contain the actual implementation. Include this netlist file into your Precision RTL project as an input file. Then include the IP core wrapper file <output file>.v|vhd in the Quartus® Prime project along with your EDIF or VQM output netlist.

The generated “gray box” netlist file, <output file>_syn.v , is always in Verilog HDL format, even if you select VHDL as the output file format.

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