Quartus® Prime Pro Edition User Guide: Third-party Synthesis
ID
683122
Date
5/23/2025
Public
1.1. About Precision RTL Synthesis Support
1.2. Precision RTL Integration Flow
1.3. Altera Device Family Support
1.4. Precision RTL Generated Files
1.5. Creating and Compiling a Project in the Precision Synthesis Software
1.6. Mapping the Design with Precision RTL
1.7. Synthesizing the Design and Evaluating the Results
1.8. Guidelines for Altera IP Cores and Architecture-Specific Features
1.9. Siemens EDA Precision* RTL Synthesis Support Revision History
1.8.1. Instantiating IP Cores With IP Catalog-Generated Verilog HDL Files
1.8.2. Instantiating IP Cores With IP Catalog-Generated VHDL Files
1.8.3. Instantiating Intellectual Property With the IP Catalog and Parameter Editor
1.8.4. Instantiating Black Box IP Functions With Generated Verilog HDL Files
1.8.5. Instantiating Black Box IP Functions With Generated VHDL Files
1.8.6. Inferring Altera IP Cores from HDL Code
2.1. About Synplify Support
2.2. Synplify Software Integration Flow
2.3. Hardware Description Language Support
2.4. Altera Device Family Support
2.5. Tool Setup
2.6. Synplify Software Generated Files
2.7. Design Constraints Support
2.8. Simulation and Formal Verification
2.9. Synplify Optimization Strategies
2.10. Guidelines for Altera IP Cores and Architecture-Specific Features
2.11. Synopsys Synplify* Support Revision History
2.12. Quartus Prime Pro Edition User Guide: Third-Party Synthesis Archives
2.10.1.1. Instantiating Altera IP Cores with IP Catalog Generated Verilog HDL Files
2.10.1.2. Instantiating Altera IP Cores with IP Catalog Generated VHDL Files
2.10.1.3. Changing Synplify’s Default Behavior for Instantiated Altera IP Cores
2.10.1.4. Instantiating Intellectual Property with the IP Catalog and Parameter Editor
2.10.1.5. Instantiating Black Box IP Cores with Generated Verilog HDL Files
2.10.1.6. Instantiating Black Box IP Cores with Generated VHDL Files
2.10.1.7. Other Synplify Software Attributes for Creating Black Boxes
2.10.3.1. Inferring Multipliers
The figure shows the HDL Analyst view of an unsigned 8 × 8 multiplier with two pipeline stages after synthesis in the Synplify software. This multiplier is converted into an ALTMULT_ADD or ALTMULT_ACCUM IP core. For devices with DSP blocks, the software might implement the function in a DSP block instead of regular logic, depending on device utilization. For some devices, the software maps directly to DSP block device primitives instead of instantiating an IP core in the .vqm file.
Figure 2. HDL Analyst View of LPM_MULT IP Core (Unsigned 8x8 Multiplier with Pipeline=2)