4.1.2. 5G LDPC Decoder Data Formats
Input Data Format
An input code block of length N consists of N loglikelihood ratio codes (LLRs): L_{0},L_{1},L_{2},...,L_{N1}. Each LLR is IN_WIDTH bits wide.
IN_WIDTH is 5 or 6. The decoder input on a single active edge of the clock is 64 LLRs. The resulting width of the input data bus to the decoder is 64*IN_WIDTH.
The decoder IP accepts punctured LLRs. You can assume that the IP punctures the first 2*Z bits of the original information block during encoding, where Z is the lifting size. The IP functionally prepends 2*Z implicit LLRs with value IN_WIDTH'b0 to the input stream of LLRs.
The number of clock cycles that the IP requires to receive the LLR values is (n_{b}  2) * ceil(Z / 64), where n_{b} is the number of columns in the parity check matrix. The value of n_{b} depends on the base graph, the information block size K, and the code rate.
sink_data[64*IN_WIDTH1:0] = sink_data[383:0] 
clock cycle  

0  1  ...  148  149  
sink_data[5:0]  L_{0}  L_{64}  ...  L_{9472}  L_{9536} 
sink_data[11:6]  L_{1}  L_{65}  ...  L_{9473}  L_{9537} 
...  ...  ...  ...  ...  ... 
sink_data[383:378]  L_{63}  L_{127}  ...  L_{9535}  L_{9599} 
sink_data[64*IN_WIDTH1:0]  clock cycle  

0  1  2  3  4  5  6  7  …  78  79  
sink_data[1*IN_WIDTH1:0*IN_WIDTH]  L_{0}  L_{64}  L_{128}  L_{192}  L_{208}  L_{272}  L_{336}  L_{400}  …  L_{4080}  L_{4144} 
…  …  …  …  …  …  …  …  …  …  …  … 
sink_data[16*IN_WIDTH1:15*IN_WIDTH]  L_{15}  L_{79}  L_{143}  L_{207}  L_{223}  L_{287}  L_{351}  L_{415}  …  L_{4095}  L_{4159} 
sink_data[17*IN_WIDTH1:16*IN_WIDTH]  L_{16}  L_{80}  L_{144}  X  L_{224}  L_{288}  L_{352}  X  …  L_{4096}  X 
…  …  …  …  X  …  …  …  X  …  …  X 
sink_data[64*IN_WIDTH1:63*IN_WIDTH]  L_{63}  L_{127}  L_{191}  X  L_{271}  L_{335}  L_{399}  X  …  L_{4143}  X 
Decoder Input LLR Symbol Format
The loglikelihood value is the logarithm of the probability that the received bit is a 0, divided by the probability that this bit is a 1. It is represented as a two’s complement number. A value of zero indicates equal probability of a 1 and a 0, which you should use for depuncturing. The decoder uses asymmetrical numeric range for LLRs including the most negative two's complement value for the chosen number of bits.
LLR (IN_WIDTH=6)  Meaning  Resulting Hard Decision 

011111  Most likelihood of a 0  0 
...  ...  ... 
000001  Lowest likelihood of a 0  0 
000000  Equal probability of a 0 or 1  1 (the convention implemented by the decoder) 
111111  Lowest likelihood of a 1  1 
...  ...  ... 
100000  Most likelihood of a 1  1 
Decoder Input Control and Output Status Signal Formats
The input mode signal, sink_mode[11:0], and the output mode signal, source_mode[11:0], have the same fields. The required input values on sink_mode are the expected output values on source_mode.
 sink_mode[11] encodes the base graph selection. The value of 0 indicates base graph 1 (BG1), and the value of 1 indicates base graph 2 (BG2).
 sink_mode[10:8] is code rate selection. Refer to Table 16.
 sink_mode[7] is enable reducedsyndrome . 0: disable; 1: enable.
 sink_mode[6] is disable early termination . 0: enable; 1: disable.
 sink_mode[5:0] is Z selection. Refer to Table 15.
sink_mode[5:0]  Z  sink_mode[5:0]  Z 

0  2  26  48 
1  3  27  52 
2  4  28  56 
3  5  29  60 
4  6  30  64 
5  7  31  72 
6  8  32  80 
7  9  33  88 
8  10  34  96 
9  11  35  104 
10  12  36  112 
11  13  37  120 
12  14  38  128 
13  15  39  144 
14  16  40  160 
15  18  41  176 
16  20  42  192 
17  22  43  208 
18  24  44  224 
19  26  45  240 
20  28  46  256 
21  30  47  288 
22  32  48  320 
23  36  49  352 
24  40  50  384 
25  44  X  X 
sink_mode[10:8]

Code Rate  Base Graph 1  Base Graph 2  

Number of Rows in Parity Check Matrix (m_{b})  Number of Columns in Parity Check Matrix (n_{b})  Number of Rows in Parity Check Matrix (m_{b})  Number of Columns in Parity Check matrix (n_{b})  
000  1/5  X  X  42  52 
001  1/3  46  68  22  32 
010  2/5  35  57  17  27 
011  1/2  24  46  12  22 
100  2/3  13  35  7  17 
101  22/30 (~3/4)  10  32  X  X 
110  22/27 (~5/6)  7  29  X  X 
111  22/25 (~8/9)  5  27  X  X 
Decoder Output Data Format
The width of the source_data[383:0] signal is 384 bits, where only the Z LSBs are valid. You can ignore the rest of the MSBs.The number of output block bits is 22*Z for BG1 and 10*Z for BG2. Hence, the IP requires 22 clock cycles for BG1 and 10 clock cycles for BG2 to output the data.
source_data[383:0] 
Clock Cycle  

0  1  ...  20  21  
source_data[0]  b_{0}  b_{384}  ...  b_{7680}  b_{8064} 
source_data[1]  b_{1}  b_{385}  ...  b_{7681}  b_{8065} 
...  ...  ...  ...  ...  ... 
source_data[383]  b_{383}  b_{767}  ...  b_{8063}  b_{8447} 
source_data[383:0]  Clock Cycle  

0  1  ...  8  9  
source_data[0]  b_{0}  b_{208}  ...  b_{1664}  b_{1872} 
...  ...  ...  ...  ...  ... 
source_data[207]  b_{207}  b_{415}  ...  b_{1871}  b_{2079} 
source_data[208]  Ignored  
...  
source_data[383] 