2. Erasure Decoder Functional Description
The Erasure Decoder does not correct errors, only erasures. It avoids the complexity of finding error locations, which Reed-Solomon decoding requires.
The design algorithm and architecture is different than a Reed-Solomon decoder. Erasure decoding is a form of encoding. It tries to fill up the input with p=n-k symbols to form a valid codeword, by fulfilling the parity equations. The parity matrix and the generator matrix define the parity equations.
The design only works with small Reed-Solomon codes, such as RS(14,10), RS(16,12), RS(12,8) or RS(10,6). For a small number of parity symbols (p < k) use this design; for a large number of parity symbols (p > k-p), you should use a generator matrix.
The erasure pattern (represented by the n-bits wide in_era input ) addresses the ROM where the design stores parity submatrices. The design only has = possible erasure patterns. Therefore, the design uses an address compression module. The design encodes the address with the number of addresses that are smaller than the address and have exactly p bits set.
The Erasure Decoder receives at its input any rate of incoming symbols, up to the total block length n per cycle for the maximum throughput. You can configure parallelism and the number of channels, so that the design multiplies the incoming symbols by the number of channels in parallel that correspond to different codewords arriving at the same time. The erasure decoder produces the full decoded codeword, including check symbols, in one cycle (several codewords for several channels).
Figure 1. Codeword Decoding
An input buffer allows you to have the number of parallel symbols per channel fewer than the total block length (n). Intel recommends you use the input bandwidth, unless the parallelism depends on your interface requirements.