Nios® V Processor Intel® FPGA IP Release Notes

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ID 683098
Date 12/19/2022
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Document Table of Contents
Document Table of Contents x
1. Nios® V Processor Intel® FPGA IP Release Notes 2. Nios® V/m Processor Intel® FPGA IP ( Intel® Quartus® Prime Pro Edition) Release Notes 3. Nios® V/m Processor Intel® FPGA IP ( Intel® Quartus® Prime Standard Edition) Release Notes 4. Archives
2. Nios® V/m Processor Intel® FPGA IP ( Intel® Quartus® Prime Pro Edition) Release Notes x
2.1. Nios® V/m Processor Intel® FPGA IP v22.4.0 2.2. Nios® V/m Processor Intel® FPGA IP v22.3.0 2.3. Nios® V/m Processor Intel® FPGA IP v21.3.0 2.4. Nios® V/m Processor Intel® FPGA IP v21.2.0 2.5. Nios® V/m Processor Intel® FPGA IP v21.1.1 2.6. Nios® V/m Processor Intel® FPGA IP v21.1.0
3. Nios® V/m Processor Intel® FPGA IP ( Intel® Quartus® Prime Standard Edition) Release Notes x
3.1. Nios® V/m Processor Intel® FPGA IP v1.0.0
4. Archives x
4.1. Intel Quartus Prime Pro Edition 4.2. Intel Quartus Prime Standard Edition
4.1. Intel Quartus Prime Pro Edition x
4.1.1. Nios V Processor Reference Manual Archives 4.1.2. Nios® V Embedded Processor Design Handbook Archives 4.1.3. Nios® V Processor Software Developer Handbook Archives
1. Nios® V Processor Intel® FPGA IP Release Notes
2. Nios® V/m Processor Intel® FPGA IP ( Intel® Quartus® Prime Pro Edition) Release Notes
3. Nios® V/m Processor Intel® FPGA IP ( Intel® Quartus® Prime Standard Edition) Release Notes
4. Archives

2.5. Nios® V/m Processor Intel® FPGA IP v21.1.1

Table 5.  v21.1.1 2021.12.13
Intel® Quartus® Prime Version Description Impact
21.4
  • Bug Fix:
    • Trigger registers accessible but triggers were not supported issue fixed.
Illegal instruction exception prompted when accessing trigger registers.
  • Added new Design Example in the Nios® V/m Processor Intel FPGA IP core parameter editor.
    • GSFI Bootloader Example Design
    • SDM Bootloader Example Design
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Level Two Title