F-Tile Interlaken Intel® FPGA IP Design Example User Guide

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ID 683069
Date 9/26/2022
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Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description 3. F-Tile Interlaken Intel® FPGA IP Design Example User Guide Archives 4. Document Revision History for F-Tile Interlaken Intel® FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Hardware and Software Requirements 1.2. Generating the Design 1.3. Directory Structure 1.4. Simulating the Design Example Testbench 1.5. Compiling and Configuring the Hardware Design Example 1.6. Testing the Hardware Design Example
2. Design Example Description x
2.1. Design Example Components 2.2. Design Example Flow 2.3. Interface Signals 2.4. Register Map 2.5. Reset
1. Quick Start Guide
2. Design Example Description
3. F-Tile Interlaken Intel® FPGA IP Design Example User Guide Archives
4. Document Revision History for F-Tile Interlaken Intel® FPGA IP Design Example User Guide

2.5. Reset

In the F-Tile Interlaken Intel® FPGA IP core, you initiate the reset (reset_n=0) and hold until the IP core returns a reset acknowledge (reset_ack_n=0). After the reset is removed (reset_n=1), the reset acknowledge returns to its initial state (reset_ack_n=1). In the design example, a rst_ack_sticky register holds the reset acknowledge assertion and then triggers the removal of the reset (reset_n=1). You can use alternative methods that fit your design needs.
Important: In any scenario where the internal serial loopback is required, you must release TX and RX of the F-tile separately in a specific order. Refer to the system console script for more information.
Figure 7. Reset Sequence in NRZ Mode
Figure 8. Reset Sequence in PAM4 Mode
Level Two Title