P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

ID 683038
Date 4/04/2024
Document Table of Contents

2.3. Simulating the Design Example

The simulation setup involves the use of a Root Port Bus Functional Model (BFM) to exercise the P-tile Avalon® Streaming IP for PCIe (DUT) as shown in the following figure.

Figure 15. PIO Design Example Simulation Testbench

For more details on the testbench and the modules in it, refer to Testbench.

The following flow diagram shows the steps to simulate the design example:

Figure 16. Procedure
  1. Change to the testbench simulation directory, <project_directory>/pcie_ed_tb/pcie_ed_tb/sim/<EDA_vendor>/simulator.
  2. Run the simulation script for the simulator of your choice. Refer to the table below.
  3. Analyze the results.
Note: P-Tile does not support parallel PIPE simulations.

The simulation reports, "Simulation stopped due to successful completion" if no errors occur.