Intel® FPGA P-Tile Avalon® Streaming IP for PCI Express* Design Example User Guide

Download PDF
ID 683038
Date 12/15/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. Design Example Description 2. Quick Start Guide 3. P-tile Avalon® Streaming IP for PCI Express* Design Example User Guide Archives 4. Document Revision History for the Intel® P-Tile Avalon® Streaming Hard IP for PCIe* Design Example User Guide
1. Design Example Description x
1.1. Functional Description for the Programmed Input/Output (PIO) Design Example 1.2. Functional Description for the Single Root I/O Virtualization (SR-IOV) Design Example 1.3. Functional Description for the Performance Design Example 1.4. Hardware and Software Requirements
2. Quick Start Guide x
2.1. Directory Structure 2.2. Generating the Design Example 2.3. Simulating the Design Example 2.4. Compiling the Design Example 2.5. Installing the Linux Kernel Driver 2.6. Running the Design Example
2.3. Simulating the Design Example x
2.3.1. Testbench
2.3.1. Testbench x
2.3.1.1. Test Driver Module 2.3.1.2. PIO Design Example Testbench 2.3.1.3. SR-IOV Design Example Testbench 2.3.1.4. Performance Design Example Testbench
2.6. Running the Design Example x
2.6.1. Running the PIO Design Example 2.6.2. Running the SR-IOV Design Example
1. Design Example Description
2. Quick Start Guide
3. P-tile Avalon® Streaming IP for PCI Express* Design Example User Guide Archives
4. Document Revision History for the Intel® P-Tile Avalon® Streaming Hard IP for PCIe* Design Example User Guide

2.6. Running the Design Example

Note: Hardware testing support for the PCIe Performance design example is not available in the 21.4 release of Intel® Quartus® Prime.
Here are the test operations you can perform on the P-Tile Avalon® -ST PCIe PIO and SR-IOV design examples:
Table 2.  Test Operations Supported by the P-Tile Avalon® -ST PCIe Design Examples
Operations Required BAR Supported by P-Tile Avalon® -ST PCIe Design Example
0: Link test - 100 writes and reads 0 Yes
1: Write memory space 0 Yes
2: Read memory space 0 Yes
3: Write configuration space N/A Yes
4: Read configuration space N/A Yes
5: Change BAR N/A Yes
6: Change device N/A Yes
7: Enable SR-IOV N/A Yes (*)
8: Do a link test for every enabled virtual function belonging to the current device N/A Yes (*)
9: Perform DMA N/A No
10: Quit program N/A Yes
Note: (*) These test operations are available only when the SR-IOV design example is selected.
Level Two Title