Why is FPGA Compilation Different? Types of SYCL* FPGA Compilation FPGA Compilation Flags Emulate and Debug Your Design Evaluate Your Kernel Through Simulation Device Selectors for FPGA FPGA IP Authoring Flow Fast Recompile for FPGA Generate Multiple FPGA Images (Linux only) FPGA BSPs and Boards Targeting Multiple Homogeneous FPGA Devices Targeting Multiple Platforms FPGA-CPU Interaction FPGA Performance Optimization Use of RTL Libraries for FPGA Use SYCL Shared Library With Third-Party Applications FPGA Workflows in IDEs
Object Manifest File Syntax of an RTL Library Restrictions and Limitations in RTL Support Intel® Stratix® 10 and Intel Agilex® 7 Design-Specific Reset Requirements for Stall-Free and Stallable RTL Libraries Reset Requirements for Stall-Free RTL Libraries Reset Requirements for Stallable RTL Libraries
Intel oneAPI DPC++ Library (oneDPL) Intel oneAPI Math Kernel Library (oneMKL) Intel oneAPI Threading Building Blocks (oneTBB) Intel oneAPI Data Analytics Library (oneDAL) Intel oneAPI Collective Communications Library (oneCCL) Intel oneAPI Deep Neural Network Library (oneDNN) Intel oneAPI Video Processing Library (oneVPL) Other Libraries
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