Installation
Toolkit Installation
IMPORTANT:
Some domain-specific toolkits require you to install the Intel oneAPI Base Toolkit first for full functionality.
Use one of the following options to get and install a toolkit package:
Toolkit Name |
Binary Installer |
Package Manager |
|---|---|---|
Intel® oneAPI Base Toolkit |
N/A |
|
Intel® HPC Toolkit (requires installation of the Intel oneAPI Base Toolkit) |
N/A |
|
Intel® Rendering Toolkit |
N/A |
Each of the binary installer types operates in various modes, which are covered later in this section.
IMPORTANT:
For FPGA support in the online/offline installer, ensure that you choose to customize your installation and select the FPGA Support Package for the Intel® oneAPI DCP++/C++ Compiler component as part of your installation.
NOTE:
When using the offline installer, you can enable full offline mode by setting the environment variable INTEL_SUPPRESS_INTERNET_CONNECTION=1. When this mode is enabled:
Installer does not send installation statistics
Download-only mode is disabled
Upgrade mode is disabled
Component Installation
You can install toolkit components as standalone via binary installer or package managers. Refer to the Single Component Downloads and Runtime Versions resource to locate a component package.
Get 32-bit Libraries
To get access to 32-bit binaries of the Intel® Integrated Performance Primitives (Intel® IPP) and Intel® oneAPI Math Kernel Library (Intel® oneMKL), install the Intel® oneAPI Base Toolkit (32-bit) add-on package from the Intel oneAPI Base Toolkit download page using the process described at Install with GUI.
To use 32-bit libraries from the Intel oneAPI Base Toolkit (32-bit) package, you need to have the same version of the Intel® oneAPI Base Toolkit or standalone libraries installed on your system.
FPGA Development Flow
For instructions on installing the Intel® oneAPI Base Toolkit components required for FPGA development, refer to Install Compiler Components for Altera FPGA Development Flows.
The following FPGA development flows are supported:
SYCL* HLS Flow
This flow targets an Intel® FPGA device to generate an RTL IP core that you integrate into your FPGA application design using the Quartus® Prime software.
FPGA Acceleration Flow
This flow targets FPGA acceleration boards and requires a third party vendor-provided BSP for deployment of your kernel.
Depending on the type of FPGA compilation you perform, you might need different software.
Both FPGA development flows require Quartus® Prime software when compiling your design for FPGA simulation or generating an FPGA hardware image. Quartus® Prime software is not required when compiling your design for FPGA emulation or to obtain the FPGA Optimization Report.
For an outline of the steps required to set up your FPGA development environment, refer to Installing the FPGA Development Environment in the Intel® oneAPI DPC++/C++ Compiler Handbook for Altera FPGAs.