Developer Reference

Migrating OpenCL™ FPGA Designs to SYCL*

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ID 767849
Date 2/07/2024
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Document Table of Contents
Document Table of Contents x
Migrating OpenCL™ FPGA Designs to SYCL* FPGA Design Flow Modify Your Design Flags, Attributes, Directives, and Extensions Histogram Design Example Walkthrough Additional Information Document Revision History for Migrating OpenCL FPGA Designs to SYCL*
Migrating OpenCL™ FPGA Designs to SYCL* x
Overview Prerequisites
Modify Your Design x
Basic Modifications Advanced Modifications
Basic Modifications x
Host Code Modification Device Code Modification
Advanced Modifications x
Host Code Modification Device Code Modification
Device Code Modification x
C++ Features in Device Code
Flags, Attributes, Directives, and Extensions x
General Information Flags FPGA Board-Specific Flags Compiler Flags Optimization Flags Memory Attributes Loop Directives Floating Point Optimizations Kernel Attributes Intra-kernel Registered Assignment Function Channels/Pipes APIs LSU Attributes
Histogram Design Example Walkthrough x
OpenCL Sample Code SYCL Sample Code SYCL Sample Code With Explicit Data Movement
Document Revision History for Migrating OpenCL FPGA Designs to SYCL* x
Notices and Disclaimers
Migrating OpenCL™ FPGA Designs to SYCL*
FPGA Design Flow
Modify Your Design
Flags, Attributes, Directives, and Extensions
Histogram Design Example Walkthrough
Additional Information
Document Revision History for Migrating OpenCL FPGA Designs to SYCL*

Intra-kernel Registered Assignment Function

The following table lists the syntax for intra-kernel registered assignment function (also referred to as kernel variables in SYCL*) supported in OpenCL and SYCL:

OpenCL SYCL Description
__fpga_reg() ext::intel::fpga_reg() Directs the compiler to insert at least one register between the operand and the return value of the function call. In general, it is not necessary to include the fpga_reg() function in your kernel code to achieve desired performance.
NOTE:

Intel® strongly recommends that you use the fpga_reg() function only if you are experienced in using the Intel® Quartus® Prime Pro Edition software performing advanced optimization for a specific target device. You must have sufficient knowledge about the placement of portions of the datapath on an FPGA device.

Parent topic: Flags, Attributes, Directives, and Extensions
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