Intel® oneAPI DPC++/C++ Compiler Developer Guide and Reference
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m, Qm
Tells the compiler which features it may target, including which instruction set architecture (ISA) it may generate.
Linux: |
-mcode |
Windows: |
/Qmcode |
code |
Indicates to the compiler a feature set that it may target, including which instruction sets it may generate. Many of the following descriptions refer to Intel® Streaming SIMD Extensions (Intel® SSE) and Supplemental Streaming SIMD Extensions (SSSE). Possible values are:
This compiler option also supports many of the -m option settings available with gcc. For more information on gcc settings for -m, see the gcc documentation. |
varies |
If option arch is not specified, the default target architecture supports Intel® SSE2 instructions. |
This option tells the compiler which features it may target, including which instruction sets it may generate.
Code generated with these options should execute on any compatible, non-Intel processor with support for the corresponding instruction set.
For compatibility with gcc, the compiler allows the following options but they have no effect. You will get a warning error, but the instructions associated with the name will not be generated. You should use the suggested replacement options.
gcc Compatibility Option |
Suggested Replacement Option |
-mfma |
-march=core-avx2 |
-mbmi, -mavx2, -mlzcnt |
-march=core-avx2 |
-mmovbe |
-march=atom -minstruction=movbe |
-mcrc32, -maes, -mpclmul, -mpopcnt |
-march=corei7 |
-mvzeroupper |
-march=corei7-avx |
-mfsgsbase, -mrdrnd, -mf16c |
-march=core-avx-i |
This option only applies to host compilation. When offloading is enabled, it does not impact device-specific compilation.
None