Intel® C++ Compiler Classic Developer Guide and Reference
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Visible to Intel only — GUID: GUID-4CC1E145-4179-4233-91B9-68AC940AC5B6
Visible to Intel only — GUID: GUID-4CC1E145-4179-4233-91B9-68AC940AC5B6
_tile_loadconfig
Synopsis
void _tile_loadconfig (const void * mem_addr)
Type | Value |
---|---|
Type | Tile |
Header file | #include <immintrin.h> |
Instruction | LDTILECFG m512 |
CPUID flags | AMXTILE |
Description
Load tile configuration from a 64-byte memory location specified by "mem_addr". The tile configuration format is specified below, and includes the tile type pallette, the number of bytes per row, and the number of rows. If the specified pallette_id is zero, that signifies the init state for both the tile config and the tile data, and the tiles are zeroed. Any invalid configurations will result in #GP fault.
Technology
AMX
Category
Application-Targeted
Operation
// format of memory payload. each field is a byte. // 0: palette_id // 1: startRow (8b) // 2-15: reserved (must be zero) // 16-17: tile0.colsb -- bytes_per_row // 18-19: tile1.colsb // 20-21: tile2.colsb // ... // 46-47: tile15.colsb // 48: tile0.rows // 49: tile1.rows // 50: tile2.rows // ... // 63: tile15.rows