Intel® Cyclone® 10 LP FPGA Evaluation Kit Help

ID 662838
Updated 1/20/2020
Version Latest




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How do I program the FPGA using the USB cable?

To program the FPGA using a USB cable, do the following:

  1. Verify the dual inline package (DIP) switch S1-4 is set to OFF. This setting enables a JTAG connection to the board via the USB connector.
  2. Using the USB cable supplied in the kit, plug the black USB Type A connector into your computer's USB port. The red cable provides extra power to the board when needed but does provide USB communication.
What kind of external power adapter do I need to power the board?

Select a 5-volt DC power adapter with a center-positive jack and the following physical dimensions:

  • Inside diameter: 2.1 mm
  • Outside diameter: 5.5 mm
Do I need to license the Cypress HyperRAM* controller IP if I use it in my design?

Yes, you need a license to compile a design with the Cypress HyperRAM* controller core. There are two configurations available:

  • Basic Edition—supports a single Cypress HyperRAM* device at 100 MHz clock speed
  • Full Edition—supports up to two Cypress HyperRAM or HyperFLASH* devices at 150 MHz clock speed

Both cores are available for free evaluation with Intel® FPGA IP Evaluation Mode licenses. These licenses let the IP run while tethered via USB cable to a PC running the Intel® Quartus® development software. Once disconnected from the PC the core will continue to run for a limited time and then stop.

For more details, see the Intel® FPGA IP Evaluation Mode user guide.

Synaptic Laboratories Licensing Brochure

Request a HyperBus Memory Controller License

Download a HyperBus Memory Controller Core

Installation Guide

Why isn’t an Ethernet controller in the FPGA design?

The initial release of the Intel® Cyclone® 10 LP FPGA kit is supported by Intel® Quartus® Prime Software Suite version 17.0. The Ethernet MAC IP core will be available starting with version 17.1 of the Intel Quartus Prime Software Suite.

Do I need a license to use the Nios® II processor core in my design?

The Nios® II processor consists of two configurable 32-bit processor cores; one is licensed and the other is free.

  • Fast core: A six-stage pipeline optimized for the highest performance optional memory management unit (MMU) or memory protection unit (MPU). This requires a license to ship in a production product, but is free for evaluation and development using the Intel FPGA IP Evaluation Mode license.
  • Economy core: Available at no cost and no license is required, this core is optimized for the smallest size.
How many power rails does this device use?

The device uses four power rails.

How do I get an example power tree?

Here is an example power tree: Intel® Cyclone® 10 LP FPGA Power Tree