Extend the Roofline Model

Published: 12/03/2021  

Last Updated: 12/03/2021

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Aleksandar Ilic
Senior researcher, HPC Architectures & Systems Group, Instituto de Engenharia de Sistemas e Computadores - Investigação e Desenvolvimento (INESC-ID)

Diogo Augusto Pereira Marques
Researcher, HPC Architectures & Systems Group, INESC-ID

INESC-ID researchers Aleksandar Ilic and Diogo Augusto Pereira Marques reveal their journey in extending roofline modeling for use in application optimization, known as the Cache-Aware Roofline Model, which has been incorporated into Intel® Advisor and recognized with an award from the High Performance Embedded Architecture and Compilation (HiPEAC) community in Europe. They are now taking this model further, tackling different types of devices, including CPUs and GPUs, with the help of Data Parallel C++ (DPC++). Using the Cache-Aware Roofline Model, developers can detect bottlenecks in their code and derive strategies to squeeze maximum performance out of their architecture.

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Product and Performance Information

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Performance varies by use, configuration and other factors. Learn more at www.Intel.com/PerformanceIndex.