Data Operand Independent Timing Instructions with MXCSR Dependent Timing
On processors listed in MXCSR Configuration Dependent Timing (MCDT), some data-independent timing vector instructions may have subtle data-dependent timing due to MXCSR configuration. Specifically, specific data values may delay instruction retirement by, at most, one cycle. This is a small enough delay that it may not be observable in common practice, but this small delay is still data-dependent timing. This data operand-dependent timing may impact software following Intel’s Guidelines for Mitigating Timing Side Channels Against Cryptographic Implementations.
On certain processors, MXCSR may also need to be configured to avoid data-dependent behavior for the instructions listed in the table below. This list is based on Intel's investigation and is current as of the date of publication. Intel will update this list if additional instructions with these characteristics are discovered.
|Table 1: Data Operand Independent Timing Instructions with MXCSR Dependent Timing