Data Operand Independent Timing Instructions

The table below lists instructions that have data-independent timing. These instructions can be used in conjunction with Data Operand Independent Timing Instruction Set Architecture Guidelines to help mitigate timing side channels. Note that these data operand independent timing instructions may have variable latency for reasons unrelated to the data values (for example, loading data from memory or the encoding of the instruction). Furthermore, an instruction being included on this list does not mean that its usage is resistant to power, thermal, or frequency-based side channels. Guidance to avoid these specific types of side channels will be provided separately in the future.