Overview
These manuals provide instructions and other resources for the architecture and programming environment of the Intel® 64 and IA-32 architectures.
Get Updates
To be notified of updates to the Intel 64 and IA-32 Architectures Software Developer Manuals, you can use a third-party service, such as Visualping.1
Hard Copies
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- Terms of Use
- The print vendor sets the order price of each volume; Intel uploads the finalized master with zero royalty.
Intel® 64 and IA-32 Architecture Software Developer Manuals
Get descriptions of the architecture and programming environment of the Intel® 64 and IA-32 architectures.
| Document | Description |
|---|---|
|
Intel 64 and IA-32 Architectures Software Developer Manual v085 25.0 MB |
Volume 1: Describes the architecture and programming environment of processors supporting IA-32 and Intel 64 architectures. Volume 2: Includes the full instruction set reference. Describes the instruction format and provides reference pages. Volume 3: Includes the full system programming guide and describes the operating-system support environment of Intel 64 and IA-32 architectures, including:
Note For performance-monitoring events, see PerfMon Events. Volume 4: Describes the model-specific registers of processors supporting IA-32 and Intel 64 architectures. |
|
Intel 64 and IA-32 Architectures Software Developer Manual v085, Documentation Changes 13.0 MB |
Describes bug fixes made to the Intel® 64 and IA-32 architectures software developer's manual between versions. Note This change document applies to all sets of the Intel 64 and IA-32 Architectures Software Developer Manuals. |
Programming Reference and Related Specifications
| Document | Description |
|---|---|
| Intel® Architecture Instruction Set Extensions Programming Reference | This document covers new instructions and features for future Intel processors. |
| Intel® Advanced Performance Extensions (Intel® APX) Architecture Specification | This document specifies the Intel APX extension of the encodings and the semantics of Intel® architecture. More Information |
| Introduction to Software Enabling with Intel APX | This document outlines the changes needed to enable Intel APX in compilers, application binary interfaces (ABI), operating systems, and hypervisors. More Information |
| Assembly Syntax Recommendations for Intel APX | Intel APX introduces several new concepts that require new notations in assembly syntax. This document discusses recommendations for the new notations. |
| Intel® Advanced Vector Extensions 10 (Intel® AVX10) Architecture Specification | This document describes the instruction set architecture for these extensions. |
| Converged Vector Instruction Set Architecture (ISA) for Intel AVX10 | Get introductory information for the converged vector ISA. |
Optimization Reference Manuals
Access open source code samples from select chapters of this manual. Intel provides additional code samples and updates to the repository as they are created and verified
These code samples are released under a Zero-Clause BSD license.
- Intel 64 and IA-32 Architectures Optimization Reference Manual, v50, Volume 1
- Earlier Generations of Intel 64 and IA-32 Processor Architectures, Throughput, and Latency, v50
- Documentation Changes for Intel 64 and IA-32 Architectures Optimization Reference Manual, v50
- Microarchitecture Instruction Throughput and Latency for Intel Processors and Processor Cores
- 4th Generation Intel® Xeon® Scalable Processor Family Instruction Throughput and Latency
- 3rd Generation Intel Xeon Scalable Processor Family Instruction Throughput and Latency
- Intel Xeon Scalable Processor Throughput and Latency
- 10th Generation Intel® Core™ Processor Instruction Throughput and Latency
- Intel Processors Based on Formerly Code Named Gracemont Microarchitecture Instruction Throughput and Latency
- Intel Atom® Processor Instruction Throughput and Latency
GitHub* Repositories
| Repository | Description |
|---|---|
| Code Examples | Contains open source code examples from select chapters of the Intel 64 and IA-32 Architectures Optimization Reference Manual. |
| Processor Topology Enumeration | These open source code examples demonstrate how to enumerate the various CPU topologies using CPUID instructions. The examples accompany the Intel® 64 Architecture Processor Topology Enumeration Technical Paper. |
| Intel® X86 Encoder Decoder | Use this software library for encoding and decoding X86 (IA-32 and Intel 64) instructions. |
Related Documentation
Access specifications, application notes, and technical papers.
| Document Title | Description |
|---|---|
| Hardware Prefetch Controls for Cores in Intel Atom® Processors | Learn about tuning methods that optimize the performance of hardware prefetchers, enabling them to increase a multicore system's performance. |
| Intel Analysis of Speculative Execution Side Channels | Get an overview of variants and related Intel security features. |
| Speculative Execution Side-Channel Mitigations | Get a detailed explanation of the security vulnerabilities and possible mitigations. |
| Complex Shadow-Stack Updates with Intel® Control-Flow Enforcement Technology (Intel® CET) |
Intel CET uses shadow stacks to ensure the correctness of certain control-flow transfers. Some control-flow transfers update a shadow stack with multiple accesses, which is complex. Certain events encountered during a complex shadow-stack update in a virtual machine may lead to unexpected behavior. Read recommendations that operating systems and virtual machine monitors can use to prevent these unexpected behaviors. These recommendations are based on CPU support from Intel. |
| Intel® Resource Director Technology (Intel® RDT) Architecture Specification | This document defines the architecture specification of the Intel RDT feature set. |
| Intel 64 Architecture Processor Topology Enumeration Technical Paper |
This technical paper covers the topology enumeration algorithm for single-socket to multiple-socket platforms using Intel 64 and IA-32 processors. The following GitHub repository has open source samples for this paper: Processor Topology Enumeration. These code samples are released under a Zero-Clause BSD license. |
| Runtime Microcode Update Technical Paper | Get descriptions for architectural enhancements and a software methodology to efficiently load microcode updates during runtime. |
| Optimize Software for x86 Hybrid Architecture | This technical document provides information on optimizing software for Intel® Core™ processors that support x86 hybrid architecture, including:
|
| Flexible Return and Event Delivery Specification | This specification describes the flexible return and event delivery (FRED) feature for the Intel 64 instruction set. |
| Intel Key Locker Specification | Learn about the software programming interface for the Intel architecture instruction set extensions for the Key Locker feature. |
| Intel® Data Streaming Accelerator (Intel® DSA) Architecture Specification | This document describes the Intel DSA architecture. |
| Intel DSA User Guide | This document provides guidelines for:
|
| Intel® In-Memory Analytics Accelerator (Intel® IAA) Architecture Specification | This document describes the architecture of Intel IAA. |
| Intel IAA User Guide | Get concise instructions for configuring Intel IAA. |
| Intel® In-Memory Analytics Accelerator Plugin for RocksDB* Storage Engine | This document describes performance improvements and cost savings for data analytics workloads using this plug-in. |
| Cassandra Enabling for Intel IAA | Performance improvements and cost savings that Intel IAA can provide when integrated with Apache Cassandra, an open source NoSQL distributed database. |
| Memory Encryption Technologies Specification for Intel Architecture | Get a description of the memory encryption support available on Intel processors. |
| Bfloat16: Hardware Numerics Definition | This document describes the bfloat16 floating-point format. |
| 5-Level Paging and 5-Level Extended Page Tables (EPT) White Paper | This document describes planned extensions to the Intel 64 architecture to expand the size of addresses that can be translated through a processor’s memory-translation hardware. |
| Machine Check Architecture (MCA) Enhancements in Intel Xeon Processors | Get a description of Enhanced MCA Logging software architecture and associated flows. |
| Intel® Carry-less Multiplication Instruction and Its Use for Computing the GCM Mode | This paper provides information on the instruction and its use for computing the Galois Hash. It also provides code examples for using PCLMULQDQ and the Intel® AES New Instructions to efficiently implement the instructions in Galois Counter Mode. |
| Performance Monitoring Unit (PMU) Sharing Guide | Get guidelines between multiple software agents that share the PMU hardware on Intel processors. |
| Intel® Virtualization Technology FlexMigration (Intel® VT FlexMigration) Application Note | This document discusses virtualization capabilities in Intel processors that support Intel VT FlexMigration uses. |
| Intel® Virtualization Technology (Intel® VT) for Directed I/O Architecture Specification | This document describes this technology. |
| Intel® Scalable I/O Virtualization Technical Specification | This document describes a scalable and composable approach for virtualizing I/O devices. |
| Secure Access of PMU by User Space Profilers | This paper proposes a software mechanism that targets performance profilers that would run at a user-space privilege to access performance-monitoring hardware. The latter requires privileged access in kernel mode securely without causing unintended interference with the software stack. |
| Timestamp-Counter Scaling for Virtualization | The information contained in this white paper has been merged into Volume 3 of the Intel® 64 and IA-32 architectures software developer's manual. |
| Intel® 64 Architecture x2APIC Specification | The information contained in this specification has been merged into Volumes 2 and 3 of the Intel® 64 and IA-32 architectures software developer's manual. |
| Intel® 64 and IA-32 Architectures Application Note TLBs, Paging-structure Caches, and their Invalidation | The information contained in this application note has been merged into Volume 3 of the Intel 64 and IA-32 Architectures Software Developer Manual. |
| Intel® 64 Architecture Memory Ordering white paper | This document was merged into Volume 3A of the Intel 64 and IA-32 Architectures Software Developer Manual. |
| Page Modification Logging for Virtual Machine Monitor white paper | The information in this white paper was merged into Volume 3 of the Intel 64 and IA-32 Architectures Software Developer Manual. |