Floating-Point Reference Sheet for Intel® Architecture
This concise technical reference sheet, attached below, covers many aspects of the IEEE Standard for Floating-Point Arithmetic (IEEE Std 754*-2008) and implementation details specific to Intel® architecture.
Binary Format Floating-Point Number and Floating-Point Classes, Encodings, and Parameters
These sections describe binary formats with parameters, encodings, and conversions between floating-point representations and their associated encodings. It also includes specific encoding information with examples for half-precision (binary16), single precision (binary32), double precision (binary64), quad precision (binary128), x87 double extended precision (an extended precision format), and bfloat16 (a non-standard format).
Operation-Specific Results and Faults for Typical Intel® SSE or Intel® AVX Scalar Instructions
The tables list special results and precomputation exceptions—invalid (I), divide-by-zero (Z), and denormal (D)—for typical Intel® SSE and Intel® AVX instructions that implement operations meant to conform to the IEEE Standard for Floating-Point Arithmetic. This includes architecture-specific details like NaN priority and denormal exceptions.
Control and Status Words
This section provides a bit-level map of the x87 floating-point control word (FPCW), x87 floating-point status word (FPSW), and the MXCSR. It also includes round control and precision control encodings as well as common abbreviations used throughout the document.
Flowchart for a Typical Intel® SSE or Intel® AVX Floating-Point Scalar Instruction
The second page walks through the behavior of a typical Intel® SSE or Intel® AVX scalar instruction that implements one of several operations meant to conform to the IEEE Standard for Floating-Point Arithmetic. The first flowchart describes the order and priority of precomputation exceptions and special cases. The last flowchart does the same but for postcomputation exceptions—precision (P), underflow (U), and overflow (O)—or for denormalized results. Both flowcharts include behavior for masked and unmasked exceptions.
For more details, see the Floating Point Reference Sheet for Intel Architecture (version 2.13)