RISC-V and SYCL* at the Heart of a New AI Acceleration Project



Many of the most dramatic advances in the evolution of computer architectures have open source origins, tapping the freedom, shared resources, and flexibility of the Commons (as fostered by organizations, including GitHub* and the Creative Commons) to build on standard frameworks and cooperative initiatives. Two key technologies, RISC-V* and SYCL*, are noteworthy examples of this design mode. They exemplify the modern movement toward developing applications that exploit the capabilities of multiarchitecture systems.

RISC-V offers an open instruction set architecture (ISA) and customizable features, which is useful for performing AI acceleration tasks, but it lacks depth in the supporting infrastructure. For example, design automation tools are in early development, so testing and verifying custom extensions is still largely a manual process.

SYCL has become the favored programming model for building applications that are portable across diverse heterogeneous environments. The unified programming environment that it supports encompasses a wide range of CPUs, GPUs, FPGAs, and accelerators, delivering great benefits to developers tasked with coding for multiarchitecture systems.

At the core of the exploratory research taking place in this area and practical applications that derive from it, oneAPI provides a model, frameworks, and advanced toolkits to meet the challenge of programming for multiarchitecture environments. SYCL is a key programming model at the center of the oneAPI initiative.

A new project uses oneAPI toolkits and libraries extensively. Project SYCLOPS was launched in January 2023 with funding provided by Horizon Europe and the participation of eight leading European organizations.


Dr. Raja Appuswamy serves as an assistant professor in the Data Science Department at the EURECOM Research Institute, located in the Sophia Antipolis Technology Park in southeast France. His current focus combines a number of past areas in his career, specifically, harnessing the performance of today’s computer hardware through algorithms and innovative storage techniques for improving the efficiency and scalability of current methods.

"My research," Raja said, "focuses on building high-performance data management systems for both traditional domains (enterprise OLTP, data warehousing) and data-intensive scientific domains (computational genomics). To this end, my research interests span several disciplines, including databases, bioinformatics, storage systems, cloud computing, and high-performance computing.

"The main technical challenge in my research," he continued, "is developing scalable algorithms and systems that can effectively exploit modern hardware to reliably store and efficiently process data." Raja’s involvement with Project SYCLOPS calls on his expertise in these areas and computing techniques he and his team members have been developing for years.

Project Description

The EURECOM Data Science department has been at the forefront of research and development efforts in AI and data science, with its world-renowned expertise and reputation in the fields of statistical machine learning, large-scale data management, data analytics, and knowledge engineering. Project SYCLOPS is a natural fit for the expertise and skillset of staff members.

According to Raja, "SYCLOPS will bring together SYCL and RISC-V standards for the first time to demonstrate groundbreaking advances in performance and scalability of extreme data analytics using a standards-based, fully open, AI acceleration approach. In doing so, we will use the experience gained in SYCLOPS to contribute back to the SYCL and RISC-V standards and foster links to respective academic, industrial, and innovator communities (RISC-V Foundation, EPI, Khronos*, ISO C++). Bringing together the two standards enables codesign, which in turn will enable a broader AI accelerator design space, and a richer ecosystem of solutions compared to current proprietary, closed solutions that force a design choice."

Asked what inspired him to become involved in this project, Raja responded, "The widespread adoption of AI and analytics has resulted in a rapidly expanding market for novel hardware accelerators that can provide energy-efficient scaling of training and inference tasks in the cloud and at the edge. Unfortunately, all popular AI acceleration solutions today use proprietary, closed hardware and software stacks, leading to a monopolization of the AI acceleration market by a few large industry experts."

Methodology and Approach

Organization members involved in Project SYCLOPS envision the development of techniques to scale AI and analytics in several data-intensive application domains, taking advantage of open standards and AI acceleration techniques. This effort brings together two complementary technologies:

  • RISC-V, a free, open ISA that can be used to gain superior performance for AI and analytics acceleration
  • SYCL, a royalty-free, cross-platform C++-based programming language to develop single-source, data-parallel code for heterogeneous processors

Raja sees Project SYCLOPS as bringing together these standards to accomplish two goals:

  1. Demonstrate groundbreaking advances in performance and scalability of extreme data analytics using a standards-based, open AI acceleration approach.
  2. Enable the development of interoperable (open and vendor neutral interfaces and APIs), trustworthy (verifiable and standards-based hardware and software), and green (by means of application-specific processor customization) AI systems.

"The developed compiler, runtime, and interpreter solutions," Raja said, "will be used to enable execution of higher-level acceleration libraries on top of an edge micro-data center that will be built, consisting of CPUs and GPUs from multiple vendors. None of these functionalities is available today in the SYCL ecosystem."

The multinational character of the project brings together experts from leading industrial and academic institutions across five countries. This includes:

  • Experts in SYCL
  • Compiler designers (from Codeplay*, an Intel acquisition)
  • SYCL runtime design (University of Heidelberg)
  • SYCL interpreter design (CERN)
  • RISC-V customization (Codasip*)
  • Energy-efficient heterogeneous edge microdatacenter assembly (HIRO*)
  • Performance modeling and profiling (INESC)
  • Scalable systems, algorithms, and applications (EURECOM, ACCELOM)

"For our application use cases," Raja said, "we will develop novel SYCL-based libraries (SYCL-ROOT, SYCL-DNN, SYCL-GAL) of various operators, algorithms and primitives that can act as drop-in, open source replacements for existing vendor-specific, closed-source libraries. In doing so, we bring together expertise in methodological machine learning, heterogeneous parallel programming, and cross-architecture performance modeling to develop domain-specific solutions that can achieve groundbreaking improvement in performance while being portable across a variety of processors."

Intel® Tools Involved in the Project

The project is slated to run from 2023 to 2026. "We are in the preliminary stages," Raja said, "where we are drafting the specifications of the hardware/software stack that will be built in the project. We are also refining the benchmarks we will use across three different application use cases (autonomous systems, high energy physics, and precision medicine) to validate the SYCLOPS stack."

Linux* will be used as the operating system throughout the project. Key Intel technologies that will play important roles in the project include:

  • Intel® oneAPI Base Toolkit
  • Intel® HPC Toolkit
  • Intel oneAPI programming tools, including Intel® VTune™ Profiler
  • Intel® Developer Cloud
  • Intel® Xeon® processors
  • Intel® GPUs
  • Intel® FPGAs

In particular, the Codeplay compiler toolchain will play an important role in the project. Raja also noted that the team is making substantial use of Intel® oneAPI Threading Building Blocks (oneTBB) and Intel® oneAPI DPC++ Library (oneDPL) .

Working with Intel has clear benefits. "We gain a broader impact and reach," Raja said, "plus the ability to contribute to a growing open hardware acceleration movement."

Interoperability across platforms is a unifying theme for the project. "Through rigorous benchmarking along various dimensions (throughput, latency, energy efficiency, scalability, and accuracy) using a variety of multivendor, multiarchitecture processors we intend to demonstrate that the SYCLOPS stack can achieve three goals."

The three primary goals defined by Raja are:

  1. To achieve groundbreaking advances in performance and scalability of extreme data analytics using hardware acceleration
  2. To provide interactive, timely discovery of useful data from heterogeneous datasets
  3. To enable the development of interoperable (open and vendor neutral interfaces and APIs), trustworthy (verifiable and standards-based hardware and software), green (via application-specific processor customization) AI systems

Closing Thoughts

Looking to the future, Raja offered these thoughts, "To improve programmer productivity, we will develop an interactive SYCL interpreter that will enable programmers to develop and run SYCL code using a Jupyter* Notebook frontend for performing ad hoc data analysis. As notebooks form a key part of the modern-day scientific reproducibility initiatives—especially for HPC/data scientists—the SYCL interpreter will provide a major step in bridging the gap between heterogeneous parallelism and reproducible analysis."

"We will also develop open source tools," he continued, "that assist in the porting of existing CUDA code to standard SYCL, and cross-architecture performance profiling tools to help developers analyze their applications with respect to accelerator utilization."

Raja’s work with Project SYCLOPS promises to deliver advances that have been important to him since the start of his career, finding techniques for incorporating the advantages of an open hardware acceleration platform—provided by RISC-V—with the benefits of open, data-parallel programming granted by SYCL. The results are likely to be embraced by many who are involved in high-performance analytics and the rising generation of AI-powered applications.

Resources and Recommendations

The Electronic Engineering Journal offers some perspective on recent enhancements to oneAPI: Intel’s Latest Version of oneAPI Takes Advantage of the New Intel® Xeon® Processor Improvements, Supports AMD* and NVIDIA*.

The fundamental characteristics of SYCL and its benefits for unifying programming across diverse architectures are described in this Intel article, Essentials of SYCL.

To help spark innovation, Intel has released AI reference kits, as discussed in this Intel newsroom article: Intel Accelerates AI Development with Reference Kits.

Semiconductor Engineering reveals how RISC-V processor cores are beginning to gain visibility in the market: RISC-V Pushes into the Mainstream.

Intel Developer Cloud for oneAPI offers free access to code from anywhere, offering cutting-edge Intel CPUs, GPUs, FPGAs, and preinstalled Intel® oneAPI Toolkits including tools, frameworks, and libraries. Sign up for this free resource and get started in minutes.

For more about the SYCLOPS project, visit the project website, X account, or LinkedIn* account.