Intel® C++ Compiler 18.0 for macOS* Release Notes for Intel® Parallel Studio XE 2018

ID 788301
Updated 11/15/2017
Version
Public

A newer version of this document is available. Customers should click here to go to the newest version.

author-image

By

Intel C++ Compiler 18.0 for macOS* Release Notes for Intel Parallel Studio XE 2018

This document provides a summary of new and changed product features and includes notes about features and problems not described in the product documentation. 

Please see the licenses included in the distribution as well as the Disclaimer and Legal Information section of these release notes for details. Please see the following links for information on this release of the Intel® C++ Compiler 18.0.

Change History

This section highlights important from the previous product version and changes in product updates.  

Changes in Update 5(Intel® C++ Compiler 18.0.5)

  • Intel® Parallel Studio XE 2018 Update 5 has been updated to include more recent versions of 3rd party components, which include functional and security updates. Users should update to the latest version.

    NOTE:  Although the Intel® Parallel Studio XE 2018 package for this update release is Update 5, the actual compiler version and directories you see will be 2018.6.xxx.  This is because of an internal update in our build process.  Be assured that the 2018.6.xxx directories and product versions 18.0.6 in packages you see during installation are indeed for the Intel® Parallel Studio 2018 Update 5 release.

Changes in Update 4(Intel® C++ Compiler 18.0.4)

  • Corrections to reported problems

Changes in Update3 (Intel® C++ Compiler 18.0.3)

Changes in Update 2 (Intel® C++ Compiler 18.0.2)

Changes in Update 1 (Intel® C++ Compiler 18.0.1)

  • Xcode* 9 and macOS* 10.13 support
  • Fixes for reported problems

Changes since Intel® C++ Compiler 17.0 (New in Intel® C++ Compiler 18.0)

Back to top

System Requirements

  • A 64-bit Intel®-based Apple* Mac* system host (development for 32-bit is still supported)
  • 2GB RAM minimum, 4GB RAM recommended
  • 3GB free disk space
  • One of the following combinations of macOS*, Xcode* and the Xcode SDK: 
    • macOS* 10.12,10.13
    • Xcode* 8.x,9.4
  • If doing command line development, the Command Line Tools component of Xcode* is required

Note: Advanced optimization options or very large programs may require additional resources such as memory or disk space.

Back to top

How to use the Intel® C++ Compiler

Parallel Studio XE 2018: Getting Started with the Intel® C++  Compiler 18.0 for macOS* at <install_dir>/documentation_2018/en/compiler_c/ps2018/get_started_mc.htm contains information on how to use the Intel® C++ Compiler from the command line and from Xcode*.

Back to top

Documentation

Product documentation is linked from <install-dir>/documentation_2018/en/compiler_c/ps2018/get_started_mc.htm.  Full documentation for all tool components is available at the Intel® Parallel Studio XE Support page.

Offline Core Documentation Removed from the Installed Image

Offline core documentation is removed from the Intel® Parallel Studio XE installed image. The core documentation for the components of Intel® Parallel Studio XE are available at the Intel® Software Documentation Library for viewing online. You can also download an offline version of the documentation from the Intel® Software Development Products Registration Center: Product List > Intel® Parallel Studio XE Documentation.

Intel-provided debug solutions

Back to top

Samples

Product samples are now available online at Intel® Software Product Samples and Tutorials

Back to top

Technical Support

If you did not register your compiler during installation, please do so at the Intel® Software Development Products Registration Center at https://lemcenter.intel.com. Registration entitles you to free technical support, product updates and upgrades for the duration of the support term.

For information about how to find Technical Support, Product Updates, User Forums, FAQs, tips and tricks, and other support information, please visit: http://www.intel.com/software/products/support/ 
Note: If your distributor provides technical support for this product, please contact them for support rather than Intel.

Back to top

New and Changed Features

__INTEL_LIBIRC_DEBUG environment variable

If OS/HW work incorrectly and libirc gets a cache size of 0 from CPUID, it may cause performance degradation. In such case user can define env. variable __INTEL_LIBIRC_DEBUG=1 to identify the root cause and get the information about OS/HW issue, e.g. export __INTEL_LIBIRC_DEBUG=1

Support for the new codenames for targeting specific cpu

Support for the following new cpuid(codenames)

  • haswell
  • broadwell
  • skylake
  • skylake_avx512
  • knl
  • knm

In the following function attributes (meaning manual targeting of those functions to the specified cpu codename): C/C++ __attribute__((cpu_dispatch( )))
C/C++ __attribute__((cpu_specific( )))
C/C++ __attribute__((vector(processor()))

monotonic and overlap keywords for ordered block in simd context

New keywords for existing #pragma omp ordered simd

  • #pragma omp ordered simd monotonic()
  • #pragma omp ordered simd overlap(expr)
  • #pragma omp simd reduction(=: list)

Please refer the Intel® C++ Compiler 18.0 User and Reference guide for more details

Support of hardware based PGO

Profile Guided Optimization (PGO) Hardware-based event sampling is a new low overhead model to get (many) benefits of PGO using the Intel® Compiler and the Intel® VTune™ Amplifier. Data collection works on systems where Intel® VTune™ Amplifier is supported.

Please refer the Intel® C++ Compiler 18.0 User and Reference guide for more details

Parallel STL for parallel and vector execution of the C++ STL

Intel(R) C++ Compiler is installed with Parallel STL, an implementation of the C++ standard library algorithms with support for execution policies.

For more information about Parallel STL, see Getting Started and Release Notes .

To learn more, please refer to article https://software.intel.com/en-us/get-started-with-pstl

Change in behavior of extract ( _mm256_extract_epi8 ) instrinics return type

Intel defined 256-bit vector intrinsics _m256_extract_epi8/epi16(__m256i a, const int index) return int instead of __int8/__int16 values.

New option -Qimf-use-svml to enforce SVML

New option forces use of SVML where currently LIBM is used, for scalar math. This guarantees bitwise-same result of computations made with vectorized code vs computations made with scalar code. With this feature the compiler vectorizes math functions in /fp:precise FP model and vectorized code produces results consistent with scalar code results. 

New /qopt-zmm-usage option

You can tune the zmm code generation done by the compiler with the new additional option -qopt-zmm-usage:low|high. The argument value of low provides a smooth transition experience from - Intel® Advanced Vector Extensions 2 (Intel® AVX2) ISA to Intel® Advanced Vector Extensions 512 (Intel® AVX-512) ISA on a Intel® Xeon® Platinum processor (formerly code name Skylake), such as for enterprise applications. Tuning for ZMM instruction use via explicit vector syntax such as #pragma omp simd simdlen() is recommended. The argument value of high is recommended for applications, such as HPC codes, that are bounded by vector computation to achieve more compute per instruction through use of the wider vector operations. The default value is low for Skylake server microarchitecture-family compilation targets and high for Intel® Core™ /Intel® Many Integrated Core Architecture (Intel® MIC Architecture) Intel® AVX-512 combined compilation targets.

CET - Control-Flow Enforcement Technology support

Control-flow Enforcement Technology (CET) defends a program from certain attacks that exploit vulnerabilities, e.g. Return-oriented Programming (ROP) and similarly Call/Jmp-oriented Programming (COP/JOP). Please refer to the Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 1: Basic Architecture for more details.

New compiler option /Qcf-potection[:keyword] introduced in the compiler to support CET.

Compile time dispatching for SVML calls

The compiler default behaviour is changed for SVML functions and a call to cpu-specific SVML entry is performed. Specifying new option -Qimf-force-dynamic-target reverts to the previous behavior and dynamic SVML dispatching is used.

Features from OpenMP* TR4 Version 5.0 Preview 1

Language features for task reductions from the OpenMP* Technical Report 4 : Version 5.0 Preview 1 specifications are now supported.

  • TASKGROUP now has the TASK_REDUCTION clause.
  • TASK includes now has the IN_REDUCTION clause
  • TASKLOOP now has the REDUCTION and IN_REDUCTION clauses

For more information, see the compiler documentation or the link to the OpenMP* Specification above.

Support for more new features from OpenMP* 4.0 or later

  • taskloop construct feature #pragma omp taskloop[clause[[,]clause]..]
  • Support for #pragma omp for linear (list [ : linear-step ])
    •  where list is either list or modifier(list)
  • Support for ref, val, and uval modifiers for the linear clause
    •  Examples:  linear(ref(p)), linear(val(i):1), linear(uval(j):1)
  • Support for #pragma omp simd simdlen(n)
  • Support for #pragma omp ordered [simd]
  • Reductions over whole arrays:  int x[n]; #pragma omp simd reduction(+:x)
  • Intel® processor clause extension added to #pragma omp declare simd (proposed; not officially part of OpenMP* 4.5)
  • support for clauses SIMD and NONMONOTONIC modifiers for #pragma omp for schedule :
    • The Intel® C++ Compiler 17.0 include SIMD and NONMONOTONICmodifiers extenstion to schedule clause to enhance user control of how interations of the for loop are divided among threads of team. See the Intel® C++ Compiler User’s Guide for more details.
  • support for array sections as list items in the reduction clause
    • reduction(reduction-identifier:list) If a list item is an array section, it is treated as if reduction clause is applied to each seperate element of the section. The elements of the private array sections will be allocated contiguously

C++17 features supported

The Intel® C++ Compiler 18.0 supports the following features under the /Qstd=c++17 (Windows*) or -std=c++17 (Linux*/macOS*) options:

  • Static assert with no message (N3928)
  • Relaxed Range based for loops (N3994)
  • Please see C++17 Features Supported by Intel® C++ Compiler for an up-to-date listing of all supported features, including comparisons to previous major versions of the compiler.

C++14 features supported

The Intel® C++ Compiler 18.0 supports the following features under the /Qstd=c++14 (Windows*) or -std=c++14 (Linux*/macOS*) options:

C++11 features supported

The Intel® C++ Compiler 18.0 supports the following features under the /Qstd=c++11 (Windows*) or -std=c++11 (Linux*/macOS*) options:

  • Support for counted range based for loops as parallel loops like omp parallel
  • Please see C++11 Features Supported by Intel® C++ Compiler for an up-to-date listing of all supported features, including comparisons to previous major versions of the compiler.

New and Changed Compiler Options

For details on these and all compiler options, see the Compiler Options section of the Intel® C++ Compiler 18.0 User's Guide.

  • All –o* options replaced by –qo* options

    All the –o* options deprecated in the previous release have been replaced with –qo* options in this release with one noted exception, there is no change to the –o option for Linux* and macOS* used to name the output file.

    On Windows*, this change impacts compiler options passed to the target compilation with the /Qoffload-option Compiler option.

    A new diagnostic is issued when any now replaced –o option is used. For example:

    $ icc -openmp example.c
    icc: command line error: option '-openmp' is not supported. Please use the replacement option '-qopenmp'

    Options affected:

    -[no-]openmp
    -openmp-lib=<arg>
    -openmp-link=<arg>
    -[no-]openmp-offload
    -[no-]openmp-simd
    -openmp-stubs
    -openmp-threadprivate=<arg>
    -openmp-report[=<level>]
    -openmp-task=<arg>
    -opt-args-in-regs=<arg>
    -[no-]opt-assume-safe-padding
    -opt-block-factor=<arg>
    -[no-]opt-calloc
    -[no-]opt-class-analysis
    -[no-]opt-dynamic-align
    -[no-]opt-gather-scatter-unroll
    -[no-]opt-jump-tables=<arg>
    -opt-malloc-options=<arg>
    -[no-]opt-matmul
    -[no-]opt-mem-layout-trans=<arg>
    -[no-]opt-multi-version-aggressive
    -[no-]opt-prefetch[=<val>]
    -opt-prefetch-distance=<arg>
    -opt-ra-region-strategy[=<arg>]
    -[no-]opt-report-embed
    -opt-report-file=<arg>
    -opt-report-filter=<arg>
    -opt-report-format=<arg>
    -opt-report-phase=<arg>
    -opt-report-routine=<arg>
    /opt-report-help
    /opt-report[=<arg>]
    /opt-report-per-object
    /opt-streaming-cache-evict=<arg>
    /opt-streaming-stores=<arg>
    /[no-]opt-subscript-in-range
    /opt-threads-per-core=<arg>

For a list of deprecated compiler options, see the Compiler Options section of the Intel® C++ Compiler 18.0 User's Guide.

Back to top

Support Deprecated

Intel® Cilk™ Plus deprecated in 18.0

Intel® Cilk™ Plus is a deprecated feature in the Intel® C++ Compiler 18.0. Prefer to use OpenMP-based syntax for offloading to the processor graphics. For more information see Migrate Your Application to use OpenMP* or Intel® TBB Instead of Intel® Cilk™

Support for 32-bit icc wrapper deprecated in 18.0

icc: remark #10421: The IA-32 target wrapper binary 'icc' is deprecated. Please use the compiler startup scripts or the proper Intel(R) 64 compiler binary with the '-Qm32' option to target the intended architecture

Support Removed

Support for installation on OS X 10.11 or earlier has been removed

Support has been removed for installation and use on these operating system versions. Intel recommends migrating to a newer version of these operating systems.

Known Limitations

spurious error with latest version of macOS* headers with std::map class

You may receive a spurious error stating “template instantiation resulted in unexpected type” while using the std::map class if you are using the latest version of the MacOS headers (Xcode 9.0 which is currently in beta). The error would look like this: /Applications/Xcode.app/Contents/Developer/Toolchains/XcodeDefault.xctoolchain/usr/include/c++/v1/_tuple(408): error: template instantiation resulted in unexpected function type of "auto (std::1::tuple_types , std::1::tuple_types )->std::1::_all<(bool)true, (bool)true> " (the meaning of a name may have changed since the template declaration – the type of the template is "auto (std::_1::tuple_types<_LArgs...> , std::1::tuple_types<_RArgs...> )->std::1::all<(std::_1::enable_if<_Trait<_LArgs, _RArgs>::value, bool>::type{true})...>") using _convertible = decltype(_do_test(_FromArgs{}, _ToArgs{})); …
This bug will be fixed in the next update. The only known workaround is to use an older version of Xcode than 9.0.

Support for OS X* 10.11 and higher

Xcode* requires explicit acceptance of Intel bundle at startup for integration to be installed
Beginning with Xcode* 6.3.2, the IDE integration for Intel® Parallel Studio XE does not complete installation until the next time Xcode is started after completing the product installation. When Xcode* is started, you will see a dialog:
 

The dialog is titled “Unexpected code bundles”, and mentions that Xcode found one or more code bundles not provided by Apple. It then has two buttons, one to “Load Bundles” and one to “Skip Bundles”. “Load Bundles” is required to be clicked to complete the Intel Parallel Studio XE IDE integration. Clicking “Skip Bundles” will cause the Intel tools to not be selectable in Xcode*.

Incompatible with the default libc++ library
Some applications are incompatible with libc++, which is currently enabled as default C++ library in the Intel® C++ Compiler 17.0. For example, the 435.gromacs and 447.dealII from SPEC CPU2006 suite. 
Please use -stdlib=libstdc++ to compile such applications.

Creating new project in Xcode* causes hardcoding of –stdlib=libc++
A new project created in Xcode* causes the hardcoding of a setting for -stdlib=libc++ even for projects that have the Intel® C++ Compiler toolset added. So setting the Intel® C++ Compiler field for the C++ Standard Library setting to libstdc++ is ineffective because libc++ overrides the setting. To change this, do the following:
1.    Select the project row in the navigator area at the left of the workspace window 
2.    In the project editor that appears, select the row that represents the project level of build settings 
3.    You should see the C++ Standard Library setting in bold, indicating that it has a custom value in this project 
4.    Select that row and press the Delete key to remove the customized value 
5.    The C++ Standard Library build property should now have the value Compiler Default
Note that you may have to follow the above steps before adding the Intel® C++ Compiler toolset to your project build rules.

Building Tachyon
For building from Xcode*, you may run into problems building the build_with_tbb configuration with llvm gcc*.  The problem will be that the libtbb.dylib cannot be found.  In this case, go to the Summary->Linked Frameworks and Libraries section, and manually add the libtbb.dylib library from the <install-dir>/tbb/lib directory

Back to top

Disclaimer and Legal Information

Optimization Notice
Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice. Notice revision #20110804

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL(R) PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. UNLESS OTHERWISE AGREED IN WRITING BY INTEL, THE INTEL PRODUCTS ARE NOT DESIGNED NOR INTENDED FOR ANY APPLICATION IN WHICH THE FAILURE OF THE INTEL PRODUCT COULD CREATE A SITUATION WHERE PERSONAL INJURY OR DEATH MAY OCCUR.

Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The information here is subject to change without notice. Do not finalize a design with this information.

The products described in this document may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an order number and are referenced in this document, or other Intel literature, may be obtained by calling 1-800-548-4725, or go to:  http://www.intel.com/design/literature.htm 

Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across different processor families. Go to: 

http://www.intel.com/products/processor%5Fnumber/

The Intel® C++ Compiler is provided under Intel's End User License Agreement (EULA). 

Please consult the licenses included in the distribution for details.

Intel, Intel logo, and Cilk are trademarks of Intel Corporation in the U.S. and other countries.

* Other names and brands may be claimed as the property of others.

Copyright © 2019 Intel Corporation. All Rights Reserved.

Back to top

 
For more complete information about compiler optimizations, see our Optimization Notice.

Product and Performance Information

1

Performance varies by use, configuration and other factors. Learn more at www.Intel.com/PerformanceIndex.