Intel® C++ Compiler 17.0 for Linux* Release Notes for Intel® Parallel Studio XE 2017

ID 788301
Updated 8/8/2016

A newer version of this document is available. Customers should click here to go to the newest version.



This document provides a summary of new and changed product features and includes notes about features and problems not described in the product documentation. 

Please see the licenses included in the distribution as well as the Disclaimer and Legal Information section of these release notes for details. Please see the following links for information on this release of the Intel® C++ Compiler 17.0.

Change History

Changes in Update 6 (Intel® C++ Compiler 17.0.5)

Changes in Update 5 (Intel® C++ Compiler 17.0.5)

Changes in Update 4 (Intel® C++ Compiler 17.0.4)

  • Updated Japanese Localization
  • Fixes for reported problems

Changes in Update 3 (Intel® C++ Compiler 17.0.3)

  • Fixes for reported problems

Changes in Update 2 (Intel® C++ Compiler 17.0.2)

  • Fixes for reported problems

Changes in Update 1 (Intel® C++ Compiler 17.0.1)

  • Localized Intel compiler documentation and diagnostic messages in Japanese language
  • Fixes for reported problems

Changes since Intel® C++ Compiler 16.0 (New in Intel® C++ Compiler 17.0)

Back to top

System Requirements

  • A PC based on an Intel® 64 architecture processor supporting the Intel® Streaming SIMD Extensions 2 (Intel® SSE2) instructions (Intel® 2nd Generation or newer Generation of Intel® Core™ i3, i5, or i7 processors and Intel® Xeon® E3 or E5 processor family, or compatible non-Intel processor)
    • Development of 64-bit applications or applications targeting Intel® MIC Architecture is supported on a 64-bit version of the OS only.  Development of 32-bit applications is now supported on a 64-bit version of the OS only.  The compiler cannot be installed on a 32-bit OS.
    • Development for a 32-bit target on a 64-bit host may require optional library components (ia32-libs, lib32gcc1, lib32stdc++6, libc6-dev-i386, gcc-multilib, g++-multilib) to be installed from your Linux distribution.
  • For Intel® MIC Architecture development/testing:
  • For offload to or native support for Intel® Graphics Technology development/testing
    • Offload is supported from 64-bit applications only
    • A 64-bit graphics driver with support for Intel® Graphics Technology (available from the Intel® Software Development Products Registration Center at You should have access to the Intel® HD Graphics Drivers for Linux* download area as part of your Intel® Parallel Studio XE registration. If you do not see this area, please contact support. The following driver versions, corresponding operating systems, and processors are supported:
    • Intel® HD Graphics Drivers for Linux* version 16.4.4 for 4th Generation Intel® Core™ Processors and 5th Generation Intel® Core™ Procesors
    • Community Enterprise Operating System (CentOS) 7.1 for 64-bit architecture
    • Red Hat Enterprise Linux (RHEL) 7.1 for 64 bit architecture
    • The following processors are supported:
      • 5th Generation Intel Core™ Processors with Intel Iris™ Graphics or Intel HD Graphics  (5500, 6000, 6100).
      • 4th Generation Intel Core™ Processors with Intel Iris™ Pro Graphics, Intel Iris Graphics or Intel HD Graphics 4200+ Series (chipset compatibility is usually not an issue for Core™ processors.)
      • Intel® Xeon® Processor E3 v3 Family with Intel® HD Graphics P4700
      • Intel® Xeon® Processor E3 v4 Family with Intel® Iris™ Pro Graphics P6300
      • Please note:
      • Chipset must have processor graphics enabled, make sure to check the datasheet.
      • Intel® Xeon® Processors require C226 chipset.
      • Intel Core processors earlier than 4th Generation are not supported
      • Intel Celeron®, Intel Pentium® and Intel Atom™ processors are not supported
  • For the best experience, a multi-core or multi-processor system is recommended
  • 2GB of RAM (4GB recommended)
  • 7.5GB free disk space for all features
  • One of the following Linux distributions (this is the list of distributions tested by Intel; other distributions may or may not work and are not recommended - please refer to Technical Support if you have questions):
    • Fedora* 24
    • Red Hat Enterprise Linux* 6, 7
    • SUSE LINUX Enterprise Server* 11, 12
    • Ubuntu* 14.04 LTS, 15.10, 16.04 LTS
    • Debian* 7.0, 8.0
    • Intel® Cluster Ready
  • Linux Developer tools component installed, including gcc, g++ and related tools
    • gcc versions 4.3 - 6 supported
    • binutils versions 2.20-2.26 supported
  • Library is required in order to use the –traceback option.  Some Linux distributions may require that it be obtained and installed separately.

Additional requirements to use the integration into the Eclipse* development environment

  • Eclipse Platform version 4.6 with:
    • Eclipse C/C++ Development Tools (CDT) 8.8 or 9.0
    • Java* Runtime Environment (JRE) 8.0 (also called 1.8) or later
  • Eclipse Platform version 4.5 with:
    • Eclipse C/C++ Development Tools (CDT) 8.7
    • Java* Runtime Environment (JRE) 7.0 (also called 1.7) or later
  • Eclipse Platform version 4.4 with:
    • Eclipse C/C++ Development Tools (CDT) 8.4-8.6
    • Java* Runtime Environment (JRE) 7.0 (also called 1.7) or


  • The Intel compilers are tested with a number of different Linux distributions, with different versions of gcc. Some Linux distributions may contain header files different from those we have tested, which may cause problems. The version of glibc you use must be consistent with the version of gcc in use. For best results, use only the gcc versions as supplied with distributions listed above. 
  • Compiling very large source files (several thousands of lines) using advanced optimizations such as -O3, -ipo and -openmp, may require substantially larger amounts of RAM.
  • The above lists of processor model names are not exhaustive - other processor models correctly supporting the same instruction set as those listed are expected to work. Please refer to Technical Support if you have questions regarding a specific processor model
  • Some optimization options have restrictions regarding the processor type on which the application is run. Please see the documentation of these options for more information.

Intel® Manycore Platform Software Stack (Intel® MPSS)

The Intel® Manycore Platform Software Stack (Intel® MPSS) may be installed before or after installing the Intel® C++ Compiler.
Using the latest version of Intel® MPSS available is recommended. It is available from the Intel® Software Development Products Registration Center at as part of your Intel® Parallel Studio XE for Linux* registration.
Refer to the Intel® MPSS documentation for the necessary steps to install the user space and kernel drivers. 

Back to top

How to use the Intel® C++ Compiler

Parallel Studio XE 2017: Getting Started with the Intel® C++  Compiler 17.0 for Linux* at <install-dir>/documentation_2017/en/compiler_c/ps2017/get_started_lc.htm. contains information on how to use the Intel® C++ Compiler from the command line and from Linux*.

The Intel® C++ Compiler for Linux* does not provide "modulefiles" for usage with the Environmental Modules software utility, but is well suited for such usage.  See Using Environment Modules with Intel Development Tools for further information.

Back to top


Product documentation is linked from <install-dir>/documentation_2017/en/compiler_c/ps2017/get_started_lc.htm.  Full documentation for all tool components is available at the Intel® Parallel Studio XE Support page.

Japanese Language Support

Intel® compilers optionally provide support for Japanese language users when the combined English-Japanese product is installed. Error messages, visual development environment dialogs and some documentation are provided in Japanese in addition to English. By default, the language of error messages and dialogs matches that of your operating system language selection. Japanese-language documentation can be found in the ja subdirectory for documentation.

Japanese language support is not provided with every update of the product.

If you wish to use Japanese-language support on an English-language operating system, or English-language support on a Japanese-language operating system, you will find instructions at Changing Language Setting to see English on a Japanese OS environment or Vice Versa on Linux*.

Back to top

Intel-provided debug solutions

Back to top


Product samples are now available online at Intel® Software Product Samples and Tutorials

Back to top

Technical Support

If you did not register your compiler during installation, please do so at the Intel® Software Development Products Registration Center at Registration entitles you to free technical support, product updates and upgrades for the duration of the support term.

For information about how to find Technical Support, Product Updates, User Forums, FAQs, tips and tricks, and other support information, please visit: 
Note: If your distributor provides technical support for this product, please contact them for support rather than Intel.

Back to top

New and Changed Features

The following features are new or significantly enhanced in this version.  For more information on these features, please refer to the documentation.

new cpu name "mic_avx512" added for 2nd generation Intel® Xeon Phi™ processor family

The new cpu name is "mic_avx512" for 2nd generation Intel® Xeon Phi™ processor family with support for Intel® Advanced Vector Extensions 512 (Intel® AVX-512) Foundation instructions, Intel® AVX-512 Conflict Detection instructions, Intel® AVX-512 Exponential and Reciprocal instructions, Intel® AVX-512 Prefetch instructions for Intel® processors, and Intel® Advanced Vector Extensions 2 (Intel® AVX2) including the RDSEED and Multi-Precision Add-Carry Instruction Extensions (ADX) instructions.
For details about the new cpu name usage, see the Intel® C++ Compiler 17.0 User's Guide.

Some C++ Compiler Header Files Moved to a Subfolder

A list of compiler header files are moved to a subfolder of existing include folder. There is no change needed to source code that uses the C++ Compiler headers. The new subfolder will be searched during compilation automatically by the compiler driver.

SIMD Data Layout Templates (SDLT) for n-Dimentional Data Array Support for Reducing gather/scatter in SIMD programs

  • For C++ AOS layout, there is no existing language extensions for programmers to annotation the AOS->SOA conversion to minimize gather/scatter generation while vectorizing the SIMD loop/functions.
  • SDLT primitive template V2 supports n-D Containers; it is designed and implemented by using C++11 feature which supports a set of primitives/methods to convert n-D AOS layout to n-D SOA layout.

Support for more new features from OpenMP* 4.0 or later

  • Support for #pragma omp for linear (list [ : linear-step ])
    • where list is either list or modifier(list)
  • Support for ref, val, and uval modifiers for the linear clause
    •  Examples:  linear(ref(p)), linear(val(i):1), linear(uval(j):1)
  • Support for #pragma omp simd simdlen(n)
  • Support for #pragma omp ordered [simd]
  • Reductions over whole arrays:  int x[n]; #pragma omp simd reduction(+:x)
  • Intel® processor clause extension added to #pragma omp declare simd (proposed; not officially part of OpenMP* 4.5)
  • support for clauses SIMD and NONMONOTONIC modifiers for #pragma omp for schedule :
    • The Intel® C++ Compiler 17.0 include SIMD and NONMONOTONICmodifiers extenstion to schedule clause to enhance user control of how interations of the for loop are divided among threads of team. See the Intel® C++ Compiler User’s Guide for more details.
  • support for array sections as list items in the reduction clause
    • reduction(reduction-identifier:list) If a list item is an array section, it is treated as if reduction clause is applied to each seperate element of the section. The elements of the private array sections will be allocated contiguously

New Intel® Xeon Phi™ offload features

  • OpenMP* 4.5 clause changes
    • for combined or composite constructs, the if clause now supports a directive name modifier:
      • if([directive-name-modifier :] scalar-expression) the if clause only applies to the semantics of the construct named by directive-name-modifier if specified; otherwise it applies to all constructs to which an if clause can apply.  Example:  #pragma omp target parallel for if(target : do_offload_compute)
    • use_device_ptr(list) clause now implemented for #pragma omp target data
    • is_device_ptr(list) clause now implemented for #pragma omp target
  • Support for combined target constructs:
    • #pragma omp target parallel
    • #pragma omp target parallel for
    • #pragma omp target simd
    • #pragma omp target parallel for simd
  • Support for new device memory APIs:
    • void* omp_target_alloc()
    • void omp_target_free()
    • int omp_target_is_present()

Annotated source listing

  • This feature annotates source files with compiler optimization reports.  The listing format may be specified as either text or html.  The location where the listing appears can be specified as the caller site, the callee site, or both sites. 

New attribute, pragma, and compiler options for code alignment for loops

  • New attribute __attribute__((code_align(n))) is provided to align functions to a power-of-two byte boundry n
  • New pragma #pragma code_align [(n)] is provided to align the subsequent loop head to a power-of-two byte boundry n
  • New compiler option -falign-loops[=n] is provided to align all loops to a power-of-two byte boundry n, or to provide no special alignment for loops -fno-align-loops (the default).

C++14 features supported

The Intel® C++ Compiler 17.0 supports the following features with compiler option /Qstd:c++14 (Windows*) or -std=c++14 (Linux*/OS X*)

  • Support C++14 variable templates (N3651)
  • Support C++14 relaxed (aka extended) constexpr (N3652)
  • Support C++14 sized deallocation (N3663)
  • Please see C++14 Features Supported by Intel® C++ Compiler for an up-to-date listing of all supported features, including comparisons to previous major versions of the compiler.

C11 features supported

The Intel® C++ Compiler 17.0 supports the following features with compiler option /Qstd:c11 (Windows*) or -std=c11 (Linux*/OS X*)

  • Support all C11 features except C11 keyword _Atomic and __attribute((atomic))
  • Please see C11 Support in Intel® C++ Compiler for an up-to-date listing of all supported features, including comparisons to previous major versions of the compiler.

New and Changed Compiler Options

For details on these and all compiler options, see the Compiler Options section of the Intel® C++ Compiler 17.0 User's Guide.

  • -f[no-]align-loops Aligns loops to a power-of-two byte boundary. 
  • -fp-model consistent Enables consistent, reproducible results for different optimization levels or between different processors of the same architecture
  • -qopt-report-annotate Enables the annotated source listing feature and specifies its format
  • -qopt-report-annotate-position Enables the annotated source listing feature and specifies the site where optimization messages appear in the annotated source in inlined cases of loop optimizations.

For a list of deprecated compiler options, see the Compiler Options section of the Intel® C++ Compiler 17.0 User's Guide.

Compiler options starting with –o are deprecated

All compiler options starting with –o are deprecated. These will be replaced by new options preceded with –q. For example, -opt-report should now be –qopt-report. This is to improve compatibility with third-party tools that expect –o<text> to always refer to output filenames.

Change in defualt behatviour of offload DEFAULTMAP

DEFAULTMAP (TOFROM:SCALAR) Local scalars do not offload by default, need “default map: scalar” clause
Causes a scalar variable to be treated as if it appeared in a MAP clause with a map-type of TOFROM . If this clause is not specified, a scalar variable is not mapped; instead it has an implicit attribute of FIRSTPRIVATE . At most one DEFAULTMAPclause can appear in the directive.

OpenMP* helper thread removed

The OpenMP* monitor thread which was used for book-keeping during program execution has been removed. However, the thread itself is user-visible with Vtune or other tools.

New /qopt-zmm-usage option

You can tune the zmm code generation done by the compiler with the new additional option -qopt-zmm-usage:low|high. The argument value of low provides a smooth transition experience from - Intel® Advanced Vector Extensions 2 (Intel® AVX2) ISA to Intel® Advanced Vector Extensions 512 (Intel® AVX-512) ISA on a Intel® Xeon® Platinum processor (formerly code name Skylake), such as for enterprise applications. Tuning for ZMM instruction use via explicit vector syntax such as #pragma omp simd simdlen() is recommended. The argument value of high is recommended for applications, such as HPC codes, that are bounded by vector computation to achieve more compute per instruction through use of the wider vector operations. The default value is low for Skylake server microarchitecture-family compilation targets and high for Intel® Core™ /Intel® Many Integrated Core Architecture (Intel® MIC Architecture) Intel® AVX-512 combined compilation targets.

Back to top

Support Deprecated

Support Removed

Red Hat Enterprise Linux 5* is not supported

Support has been removed for installation and use on these operating system versions. Intel recommends migrating to a newer version of these operating systems.

GFX offload support for 3rd Generation Intel® Core™ Processors is not supported

GFX offload support to processor graphics for 3rd Generation Intel® Core™ Processors has been removed in Intel® C++ Compiler 17.0.

Intel® HD Graphics Drivers for Linux* version 16.3.2 for 3rd and 4th Generation Intel® Core™ Processors are not supported.
Support for the 16.3.2 driver has removed.  Intel recommends migrating to the 16.4.2 driver and its supporting operating system (either CentOS* 7.1 or RHEL 7.1) for systems based on 4th Generation Intel® Core™ Processors.

Installation on 32-bit hosts has been removed

Installation on 32-bit hosts has been removed in this release. Support for generating code for 32-bit targets is supported on 64-bit hosts (only) via compiler option -m32.

_GFX_enqueue has been removed

_GFX_enqueue has been removed and should be replaced with _GFX_offload 

Back to top

Known Limitations

Pointer Checker requires a dynamic runtime library

When using the -check-pointers option, the runtime library must be linked in. When using options like -static or -static-intel with -check-pointers, be aware that this dynamic library will be linked in regardless of your settings. See the article at for more information.

Known Issues with Intel® Many Integrated Core Architecture (Intel® MIC Architecture)

  • Set MIC_LD_LIBRARY_PATH before loading shared libraries containing offloaded code

    When loading a shared object within your program with dlopen, the setting of the MIC_LD_LIBRARY_PATH variable is required in order to pick up the *.so if the .so contains offload.  This is true even if the .so is brought in with a relative or full path (i.e. dlopen("../../", <flag>))

  • Using offload code in shared libraries requires main program to be linked with -qoffload=mandatory or -qoffload=optional option

    There is initialization required for offload that can only be done in the main program. For offload code in shared libraries, this means that the main program must also be linked for offload so that the initialization happens. This will happen automatically if the main code or code statically linked with the main program contains offload constructs. If that is not the case, you will need to link the main program with the -qoffload=mandatory or -qoffload=optional compiler options.
  • Missing symbols not detected at link time for the offload compilation model

    -offload-option,mic,compiler,"-z defs" is no longer needed to detect missing symbols at link time.
  • *MIC* tag added to compile-time diagnostics

    The compiler diagnostics infrastructure is modified to add an additional offload *MIC* tag to the output message to allow differentiation from the target (Intel® MIC Architecture) and the host CPU compilations. The additional tag appears only in the target compilation diagnostics issued when compiling with offload extensions for Intel® MIC Architecture.

    In the examples below the sample source programs trigger identical diagnostics during both the host CPU and Target Intel® MIC Architecture compilations; however, some programs will generate different diagnostics during these two compilations. The new tag permits easier association with either the CPU or Target compilation

    $ icc -c sample.c

    sample.c(1): warning #1079: *MIC* return type of function "main" must be "int"
    void main()
    sample.c(5): warning #120: *MIC* return value type does not match the function type
      return 0;
    sample.c(1): warning #1079: return type of function "main" must be "int"
     void main()
    sample.c(5): warning #120: return value type does not match the function type
      return 0;

  • Runtime Type Information (RTTI) not supported

    Runtime Type Information (RTTI) is not supported under the Virtual-Shared memory programming method; specifically, use of dynamic_cast<> and typeid() is not supported.
  • Direct (native) mode requires transferring runtime libraries like to coprocessor

    The Intel® Manycore Platform Software Stack (Intel® MPSS) no longer includes Intel compiler libraries under /lib, for example the OpenMP* library,

    When running OpenMP* applications in direct mode (i.e. on the coprocessor card), users must first upload (via scp) a copy of the Intel® MIC Architecture OpenMP* library (<install_dir>/compilers_and_libraries_2016/linux/lib/mic/ to the card (device names will be of the format micN, where the first card will be named mic0, the second mic1, and so on) before running their application.

    Failure to make this library available will result in a run-time failure like:

    /libexec/ Shared object "" not found, required by "sample"

    This can also apply to other compiler runtimes like The required libraries will depend on the application and how it’s built.
  • Calling exit() from an offload region

    When calling exit() from within an offload region, the application terminates with an error diagnostic “offload error: process on the device 0 unexpectedly exited with code 0

Known issues for offload to Intel® Graphics Technology

  • Host-side execution of offload code is not parallelized

    The compiler will generate both a target and host version of the parallel loop under #pragma offload. The host version is executed when the offload cannot be performed (usually when the target system does not have a unit with Intel® Graphics Technology enabled).The parallel loop must be specified using the parallel syntax of cilk_for or an Array Notation statement, which has parallel semantics for offload. The target version of the loop will be parallelized for target execution, but there is a current limitation where the host-side back-up version of the parallel loop will not be parallelized. Please be aware this can affect the performance of the back-up code execution significantly when offload execution does not happen in the case of cilk_for use. Array notation does not currently generate parallel code on the host, so performance should not differ here in that case. This is a known issue that may be resolved in a future product release.
  • If multiple processes running with non-root privilege try to offload there may be sporadic fails.

    You may see sporadic fails if multiple processes (with non-root privilege) try to offload. Only the first process that opens /dev/dri/card0 can pass DRM authentication. Only the first process to open /dev/dri/card0 has master privilege.  “Root” or “master” privilege is needed to pass the DRM authentication. That is why all processes pass through when running with root privilege, but only one of them passes with non-root privilege. This is a known restriction for Linux*.

    Possible workarounds
    • Execute each process serially.
    • Execute as root
  • Other known limitations with offload to Intel® Graphics Technology
    • In the offloaded code, the following are not allowed:
      • Exception handling
      • RTTI
      • longjmp/setjmp
      • VLA
      • Variable parameter lists
      • Virtual functions, function pointers, or other indirect calls or jumps
      • Shared virtual memory
      • Data structures containing pointers, such as arrays or structs
      • Globals with pointer or reference type
      • OpenMP*
      • cilk_spawn or cilk_sync
      • Intel® Cilk™ Plus reducers
      • ANSI C runtime library calls (with the exception of SVML, math.h, and mathimf.h calls and a few others)
    • 64-bit float and integer operations are inefficient

Intel® Cilk™ Plus Known Issues

  • Static linkage of the runtime is not supported 

    Static versions of the Intel® Cilk™ Plus library are not provided by design.  Using -static-intel to link static libraries will generate an expected warning that the dynamic version of the of Intel® Cilk™ Plus library,, is linked.

    $ icc -static-intel sample.c

    icc: warning #10237: -lcilkrts linked in dynamically, static library not available

    Alternatively, you can build the open source version of Intel Cilk Plus with a static runtime.  See for information on this implementation of Intel Cilk Plus. Any issues must be reported using the dynamic version of the Intel® Cilk™ Plus library.

Guided Auto-Parallel Known Issues

  • Guided Auto Parallel (GAP) analysis for single file, function name or specific range of source code does not work when Whole Program Interprocedural Optimization (-ipo) is enabled

SPEC CPUv6 runtime bus error seen on Red Hat Enterprise Linux* 6 with the Intel® IA-32 C++ compiler

  • If the SPEC CPUv6 benchmark (currently in development) is compiled with the Intel® IA-32 C++ compiler and then run with restricted stack and/or virtual memory limits using the ulimit command e.g., ulimit -s 2067152 -v 15000000, bus errors may be seen.  Although this has only been observed on this benchmark, it may apply to other applications.  A known workaround is to set these parameters to unlimited.

GCC 6.0 is not supported

  • GCC 6.0 is currently in development and is not supported for use with  Intel® C++ Compiler 16.0 Update 2.  If the compiler is used with GCC 6.0 to compile C++ files, the following informational error will be provided: "Error #3802: Version 16.0 Update 2 is incompatible with GNU versions greater than or equal to 6.0, due to an incomplete implementation of SFINAE which is used extensively in gcc6 headers. If you wish to proceed, use option -wd3802"

Spurious error when a call to a template dependent function is made in a decltype expression in an out-of-line definition for a late-specified return type


  • This is a known regression in Intel® C++ Compiler 16.0 Update 2.  An example is:
  • template <class T>
    struct C {
      int then(int*,int*);
      template <class T2>
      auto then(T2 arg) -> decltype(this->then(&arg, &arg));
    template <class T>
    template <class T2>
    auto C<T>::then(T2 arg) -> decltype(this->then(&arg, &arg)) { return 0; }
    void foo() {
       C<int> f;

    To work around this problem, the definition can be moved inline, or the use of a late-specified return type should be avoided (by explicitly declaring the return type). 

Boost issue with c++14 relaxed constexpr

  • If you are using Boost in -std=c++14 mode and you see compilation errors that seem to be related to the constexpr feature, try defining BOOST_NO_CXX14_CONSTEXPR in boost_1_59_0/boost/config/compiler/gcc.hpp.  To do this you should change these lines (around line 256):
  • #if !defined(__cpp_constexpr) || (__cpp_constexpr < 201304)
    #  define BOOST_NO_CXX14_CONSTEXPR


    //#if !defined(__cpp_constexpr) || (__cpp_constexpr < 201304)
    #  define BOOST_NO_CXX14_CONSTEXPR

Back to top

Disclaimer and Legal Information

Optimization Notice
Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice. Notice revision #20110804


Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The information here is subject to change without notice. Do not finalize a design with this information.

The products described in this document may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an order number and are referenced in this document, or other Intel literature, may be obtained by calling 1-800-548-4725, or go to: 

Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across different processor families. Go to:

The Intel® C++ Compiler is provided under Intel’s End User License Agreement (EULA). 

Please consult the licenses included in the distribution for details.

Intel, Intel logo, Pentium, Core, Atom, Iris, Xeon, Xeon Phi, and Cilk are trademarks of Intel Corporation in the U.S. and other countries.

* Other names and brands may be claimed as the property of others.

Copyright © 2017 Intel Corporation. All Rights Reserved.

Back to top

For more complete information about compiler optimizations, see our Optimization Notice.