Explore DPC++ Through Intel® FPGA Code Samples

Introduction

This guide aims to help you understand the following:

• How to navigate the Intel® FPGA DPC++ code samples in a coherent manner that builds on complexity and use-case. 
• How to get your first oneAPI application on the FPGA with the help of six essential FPGA code samples.

To aid you in your learning and to help you navigate through the DPC++ FPGA tutorials folders, use the following dependency diagram, which illustrates the dependencies between the tutorials:

NOTE:  The Intel® oneAPI DPC++ FPGA Optimization Guide, Chapter 1: Introduction To FPGA Design Concepts covers fundamental FPGA concepts, and it is a prerequisite for all FPGA-specific code samples. 

Prerequisites

• You are already familiar with SYCL* concepts and application programming interfaces (APIs) as described in the SYCL 2020 Provisional Specification by the Khronos* Group. The recommended resource for learning SYCL* language is the open-access book Data Parallel C++: Mastering DPC++ for Programming of Heterogeneous Systems Using C++ and SYCL. For additional information, refer to the SYCL* Specification version 1.2.1.
• You have experience in creating SYCL* applications. For more information, refer to the Intel® oneAPI Programming Guide.
• You have read the Intel® oneAPI DPC++ FPGA Optimization Guide, Chapter 1: Introduction To FPGA Design Concepts, which is a recommended reading if you want to develop on FPGAs. This is also a prerequisite for understanding most of the FPGA tutorials. To achieve the highest performance of your Data Parallel C++ (DPC++) application for FPGAs, you should become familiar with the underlying hardware and understand the compiler optimizations that convert and map your DPC++ application to FPGAs.

Build and Run a Sample Project

To compile the FPGA tutorials, you must either download and install the Intel® oneAPI Base Toolkit and the Intel® FPGA Add-on for oneAPI Base Toolkit, or have an account on the Intel® DevCloud for oneAPI. 

Refer to the following links to get started with the Intel® oneAPI Base Toolkit guide via the command-line interface (CLI) or integrated development environment (IDE):

• Build and Run a Sample Project Using the Command Line:
  • Linux*
  • Windows*
• Build and Run a Sample Project Using an IDE:
  • Linux (Eclipse* or Visual Studio* Code)
  • Windows (Visual Studio*)
• GitHub (Each FPGA sample has a specific Git repository link. Refer to the following sections for additional information.)

Essential FPGA Code Samples

The following FPGA samples represent a selection of useful tutorials suitable to get you started on your first oneAPI application on the FPGA: 

Sample 1: FPGA Compile Flow

This sample introduces the most commonly used compilation flow targeting Intel® FPGA devices and describes when to use each flow.

The following flows are described in the sample:

​Key concepts covered in this sample: 

• How and why compiling DPC++ to FPGA differs from CPU and GPU
• FPGA device image types and when to use them
• Compile flags used to target FPGA

​Sample 2: Save Development Time

This sample demonstrates how to use the device link mechanism in your FPGA compilation flow to save development time.

Intel® oneAPI DPC++/C++ Compiler supports only the ahead-of-time compilation for FPGA, which means that an FPGA device image is generated at compile time. FPGA device image generation process can take hours to complete. Therefore, if the host and device code are compiled together and a change in the host code is made, the entire source code is subject to this time-consuming process.

The device link mechanism allows you to separate device code compilation and host code compilation. When the code change applies only to host-only files, an FPGA device image is not regenerated, and the lengthy compile time is avoided.

Key concepts covered in this sample: 

• Why you should separate host and device code compilation in your FPGA project
• How to use the -reuse-exe flag and device link methods
• Which method to choose for your project

Sample 3: Avoid Aliasing of Kernel Arguments

This sample demonstrates the use of the DPC++ [[intel::kernel_args_restrict]] kernel attribute, which you can apply when you can guarantee that kernel arguments do not alias (similar to restrict in C++).

Pointer aliasing occurs when the same memory location is accessed using different names (i.e., variables). Due to pointer aliasing, the compiler must be conservative about optimizations that reorder, parallelize, or overlap operations, which could alias. Using the kernel_args_restrict attribute enables more aggressive compiler optimizations and often improves kernel performance on FPGA. 

Key concepts covered in this sample: 

• The problem of pointer aliasing and its impact on compiler optimizations
• The behavior of the kernel_args_restrict attribute and when to use it on your kernel
• The effect this attribute can have on your kernel's performance on FPGA

Sample 4: Optimize by Improving Loop Throughput 

This sample demonstrates a simple example of unrolling loops to improve the throughput of a DPC++ FPGA program.

Loop unrolling is a mechanism to increase program parallelism by duplicating the compute logic within a loop, which allows you to increase your design's throughput.

Key concepts covered in this sample:

• Basics of loop unrolling
• Unrolling loops in your program
• Determining the correct unroll factor for your program

Sample 5: Transfer Data with Pipes

This sample demonstrates how to transfer data between kernels using the pipes abstraction. 

Key concepts covered in this sample: 

• The basics of the FPGA-specific DPC++ pipes extension
• How to declare and use pipes in a DPC++ program

Sample 6: Improve Performance with Double Buffering  

This sample demonstrates how to parallelize host-side processing and buffer transfers between host and device with kernel execution and improve overall application performance.

Key concepts covered in this sample: 

• The double buffering optimization technique
• Determining when double buffering is beneficial
• How to measure the impact of double buffering 

Next Steps

After going through the above samples, you can peruse the rest of the DPC++ FPGA samples (tutorials or reference designs) based on the dependency diagram. When going through the tutorials, do note that many of them build on concepts from other tutorials. You can also refer to the following resources:

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