Development Reference Guides

Contents

ax, Qax

Tells the compiler to generate multiple, feature-specific auto-dispatch code paths for Intel® processors if there is a performance benefit.

Syntax

Linux:
-ax
code
Windows:
/Qax
code
Arguments
code
Indicates to the compiler a feature set that it may target, including which instruction sets it may generate. The following descriptions refer to Intel® Streaming SIMD Extensions (Intel® SSE) and Supplemental Streaming SIMD Extensions (SSSE). Possible values are:
ALDERLAKE
AMBERLAKE
BROADWELL
CANNONLAKE
CASCADELAKE
COFFEELAKE
COOPERLAKE
GOLDMONT
GOLDMONT-PLUS
HASWELL
ICELAKE-CLIENT
(or
ICELAKE
)
ICELAKE-SERVER
IVYBRIDGE
KABYLAKE
KNL
KNM
ROCKETLAKE
SANDYBRIDGE
SAPPHIRERAPIDS
SILVERMONT
SKYLAKE
SKYLAKE-AVX512
TIGERLAKE
TREMONT
WHISKEYLAKE
May generate instructions for processors that support the specified Intel® processor or microarchitecture code name.
Keywords
KNL
and
SILVERMONT
are only available on Windows* and Linux* systems.
Keyword
ICELAKE
is deprecated and may be removed in a future release.
COMMON-AVX512
May generate Intel® Advanced Vector Extensions 512 (Intel® AVX-512) Foundation instructions, Intel® AVX-512 Conflict Detection Instructions (CDI), as well as the instructions enabled with CORE-AVX2.
CORE-AVX512
May generate Intel® Advanced Vector Extensions 512 (Intel® AVX-512) Foundation instructions, Intel® AVX-512 Conflict Detection Instructions (CDI), Intel® AVX-512 Doubleword and Quadword Instructions (DQI), Intel® AVX-512 Byte and Word Instructions (BWI) and Intel® AVX-512 Vector Length extensions, as well as the instructions enabled with CORE-AVX2.
CORE-AVX2
May generate Intel® Advanced Vector Extensions 2 (Intel® AVX2), Intel® AVX, SSE4.2, SSE4.1, SSE3, SSE2, SSE, and SSSE3 instructions for Intel® processors.
CORE-AVX-I
May generate
Float-16 conversion instructions and
the RDRND instruction, Intel® Advanced Vector Extensions (Intel® AVX), Intel® SSE4.2, SSE4.1, SSE3, SSE2, SSE, and SSSE3 instructions for Intel® processors.
AVX
May generate Intel® Advanced Vector Extensions (Intel® AVX), Intel® SSE4.2, SSE4.1, SSE3, SSE2, SSE, and SSSE3 instructions for Intel® processors.
SSE4.2
May generate Intel® SSE4.2, SSE4.1, SSE3, SSE2, SSE, and SSSE3 instructions for Intel processors.
SSE4.1
May generate Intel® SSE4.1, SSE3, SSE2, SSE, and SSSE3 instructions for Intel® processors.
SSSE3
May generate SSSE3 instructions and Intel® SSE3, SSE2, and SSE instructions for Intel® processors. This replaces value T, which is deprecated.
SSE3
May generate Intel® SSE3, SSE2, and SSE instructions for Intel® processors.
SSE2
May generate Intel® SSE2 and SSE instructions for Intel® processors.
You can specify more than one
code
value. When specifying more than one
code
value, each value must be separated with a comma. See the Examples section below.
Default
OFF
No auto-dispatch code is generated. Feature-specific code is generated and is controlled by the setting of the following compiler options:
  • Linux*:
    -m
    and
    -x
  • Windows*:
    /arch
    and
    /Qx
Description
This option tells the compiler to generate multiple, feature-specific auto-dispatch code paths for Intel® processors if there is a performance benefit. It also generates a baseline code path. The Intel feature-specific auto-dispatch path is usually more optimized than the baseline path. Other options, such as
O3
, control how much optimization is performed on the baseline path.
The baseline code path is determined by the architecture specified by options
-m
or
-x
(Linux*) or options
/arch
or
/Qx
(Windows*). While there are defaults for the
[Q]x
option that depend on the operating system being used, you can specify an architecture and optimization level for the baseline code that is higher or lower than the default. The specified architecture becomes the effective minimum architecture for the baseline code path.
If you specify both the
[Q]ax
and
[Q]x
options, the baseline code will only execute on Intel® processors compatible with the setting specified for the
[Q]x
.
If you specify both the
-ax
and
-m
options (Linux) or the
/Qax
and
/arch
options (Windows), the baseline code will execute on non-Intel® processors compatible with the setting specified for the
-m
or
/arch
option.
A Non-Intel® baseline and an Intel® baseline have the same set of optimizations enabled, and the default for both is SSE4.2 for x86-based architectures.
If you specify both the
-ax
and
-march
options (Linux), or the
/Qax
and
/arch
options (Windows), the compiler will not generate Intel-specific instructions. This is because specifying
-march
disables
-ax
and specifying
/arch
disables
/Qax
.
The
[Q]ax
option tells the compiler to find opportunities to generate separate versions of functions that take advantage of features of the
specified instruction features
.
If the compiler finds such an opportunity, it first checks whether generating a feature-specific version of a function is likely to result in a performance gain. If this is the case, the compiler generates both a feature-specific version of a function and a baseline version of the function. At run time, one of the versions is chosen to execute, depending on the Intel® processor in use. In this way, the program can benefit from performance gains on more advanced Intel processors, while still working properly on older processors and non-Intel processors. A non-Intel processor always executes the baseline code path.
You can use more than one of the feature values by combining them. For example, you can specify
-axSSE4.1,SSSE3
(Linux) or
/QaxSSE4.1,SSSE3
(Windows). You cannot combine the old style, deprecated options and the new options. For example, you cannot specify
-axSSE4.1,T
(Linux) or
/QaxSSE4.1,T
(Windows).
This option only applies to host compilation. When offloading is enabled, it does not impact device-specific compilation.
Product and Performance Information
Performance varies by use, configuration and other factors. Learn more at www.Intel.com/PerformanceIndex.
Notice revision #20201201
IDE Equivalent
Visual Studio:
Code Generation > Add Processor-Optimized Code Path
Eclipse:
Code Generation > Add Processor-Optimized Code Path
Xcode:
Code Generation > Add Processor-Optimized Code Path
Alternate Options
None
Examples
The following shows an example of how to specify this option:
The following shows an example of how to specify more than one
code
value:
Note that the comma-separated list must have no spaces between the names.

Product and Performance Information

1

Performance varies by use, configuration and other factors. Learn more at www.Intel.com/PerformanceIndex.