Introduction
| IP Core | IP Core Category |
|---|---|
| Nios V Soft Processor FPGA IP - G Core | Embedded Processor |
| altera_avalon_onchip_memory2 | Other |
| altera_avalon_jtag_uart | Other |
| System ID | Other |
Detailed Description
This example design includes a Nios V/g embedded processor connected to the OCM and JTAG UART IP.
The objective of the design is to write and read into specific locations of On Chip RAM. This implementation of On Chip RAM uses the Avalon interface.
Please refer to the document for details about the design.
Prepare the design template in the Quartus Prime software GUI
Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. You can simply double click on the <project>.par file and Quartus will launch that project.