Introduction
| IP Core | IP Core Category |
|---|---|
| Nios V/m soft processor core | Embedded Processor |
| On Chip RAM - II | Other |
| JTAG UART | Other |
| SYSID | Other |
| Interval Timer | Other |
Detailed Description
This design example includes a Nios® V/m embedded processor connected to the Interval Timer IP to issue alarm-based interrupt to the Nios V/m core.
The objective of the design is to demonstrate the interrupt behavior and handling by the Nios V/m embedded processor. Once the interrupt is issued; the Nios V/m prints the system ID of the SYS ID peripheral core.
Please refer to the document for details about the design.
Prepare the design template in the Quartus Prime software GUI
Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. You can simply double click on the <project>.par file and Quartus will launch that project.