Introduction
This design enables a user to perform lane margining on the R-Tile PCIe HIP. Control to the design is supported by the PCIe link itself. A small application will need to be developed to configure, launch, and retrieve lane margining results. Pseudo code is included in this user guide as an example for the application. The small application is based on the PCIe Linux Kernel driver that ships with our R-Tile PCIe PIO Design Example. There are two major components to this tool: FPGA RTL Design and the lane margining algorithm written in C++. The solution includes source code. The source code will allow a user to customize the tool for their specific R-Tile use case.
Development Kit
IP Cores
(1)
| IP Core | IP Core Category |
|---|---|
| Nios V/g Processor | Embedded Processor |
Detailed Description
PCIe Lane Margining Design Block Diagram:
Please refer to the document for details about the design.
Prepare the design template in the Quartus Prime software GUI
Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. You can simply double click on the <project>.par file and Quartus will launch that project.