Introduction
This design example configures the F-tile PMA and FEC Direct PHY IP for passive optical network (PON) applications.
Development Kit
IP Cores
(10)
| IP Core | IP Core Category |
|---|---|
| Multiply Adder Intel FPGA IP | Arithmetic |
| Configuration Clock Intel FPGA IP | Configuration and Programming |
| Clock Control Intel FPGA IP | Clocks; PLLs and Resets |
| F-tile PMA/FEC Direct PHY Intel FPGA IP | Transceiver PHY |
| F-tile Reference and System PLL Clocks Intel FPGA IP | Transceiver PHY |
| Reset Release Intel FPGA IP | Configuration and Programming |
| RAM: 2-PORT Intel FPGA IP | On Chip Memory |
| Platform Designer | Other |
| FIFO Intel FPGA IP | On Chip Memory |
| JTAG to Avalon Master Bridge Intel FPGA IP | Memory Mapped |
Detailed Description
This design example is developed with Intel Quartus® Prime Pro Edition Design Software Version 23.1 and targets Intel Agilex® 7 FPGA I-Series Transceiver-SoC Development Kit. This design example configures the F-tile PMA and FEC Direct PHY IP for Passive Optical Network (PON) application. An ONT Burst Generator and an OLT Burst Receiver are implemented. The bursts sent from ONT will be loopback to OLT via QSFP-DD connector.