Introduction
This design example uses an Intel Agilex® 7 FPGA to demonstrate the implementation of the following three different I/O phase-locked loop (PLL) reconfiguration options using the IOPLL Reconfig Intel® FPGA IP core:
(1) .mif streaming
(2) Advanced mode
(3) Clock gating
This design example consists of the IOPLL, IOPLL Reconfig, In-System Sources & Probes, and Reset Release Intel FPGA IP cores.
IP Cores
(4)
| IP Core | IP Core Category |
|---|---|
| IOPLL Intel FPGA IP | Other |
| IOPLL Reconfig Intel FPGA IP | Other |
| In-System Sources & Probes Intel FPGA IP | Other |
| Reset Release Intel FPGA IP | Other |
Detailed Description
This design example uses a AGFB014R24A2E3VR0 device to demonstrate the implementation of the following three different I/O PLL reconfiguration option using the IOPLL Reconfig IP core.
• .mif streaming
• Advanced mode
• Clock gating
This design example consists of the IOPLL IP core, IOPLL Reconfig IP core, and In-System Sources & Probes Intel FPGA IP core.