Agilex™ 7 FPGA – Nios® V/m Processor OCM to OCM Design Example

Introduction

This design example shows on-chip memory (OCM) access using the Nios® V processor.

Device Family	Intel Agilex® 7 FPGAs and SoC FPGAs F-Series
Quartus Edition	Intel® Quartus® Prime Pro Edition
Quartus Version	22.4
Other Tags	Validated in Quartus and Board

IP Cores (3)

IP Core	IP Core Category
Nios V Soft Processor FPGA IP - M Core	Other
altera_avalon_onchip_memory2	Other
altera_avalon_jtag_uart	Other

The Nios V Processor IP communicates with the on-chip RAM and reads/writes to specific memory locations as specified in code.

The UART IP then prints the necessary statements.

Device Family	Intel Agilex® 7 FPGAs and SoC FPGAs F-Series
Quartus Edition	Intel® Quartus® Prime Pro Edition
Quartus Version	22.4
Other Tags	Validated in Quartus and Board