Introduction
This design example shows on-chip memory (OCM) access using Nios® V/m Processor.
IP Cores
(3)
| IP Core | IP Core Category |
|---|---|
| Nios V Soft Processor FPGA IP - M Core | Embedded Processor |
| altera_avalon_onchip_memory2 | Other |
| altera_avalon_jtag_uart | Other |
Detailed Description
This example design includes a Nios® V/m embedded processor connected to the OCM and JTAG UART IP.
The objective of the design is to write and read into specific locations of On Chip RAM. This implementation of On Chip RAM uses the Avalon interface.
