Intel® Cyclone® 10 LP FPGA – Synaptic Labs' Hyperbus Memory Controller IP Tutorial 003

Intel® Cyclone® 10 LP FPGA – Synaptic Labs' Hyperbus Memory Controller IP Tutorial 003

715001
8/22/2017

Introduction

This reference design demonstrates how to build a clean-slate Nios® II processor system with HyperRAM using Synaptic Labs' Hyperbus Memory Controller (HBMC) intellectual property (IP) core on the Intel® Cyclone® 10 LP FPGA Evaluation Kit. Most HBMC customers using this board will want to start with the first tutorial. In this tutorial, you will build a Nios II processor-based embedded hardware system, download it to the development board, and run software programs written in 'C'. By the end of the session, you will have gained experience in how to build and run your own embedded system in an Intel Cyclone 10 LP device. This reference design is actively maintained by Synaptic Laboratories Ltd. Includes a free trial IP.

Design Details

Device Family

Intel® Cyclone® 10 LP FPGA

Quartus Edition

Intel® Quartus® Prime Standard Edition

Quartus Version

17.0

IP Cores (0)

Detailed Description

Prepare the design template in the Quartus Prime software GUI (version 14.1 and later)


Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.


The second means to bring up the project template is through the New Project Wizard (File -> New Project Wizard). After entering the project name and folder on the first panel, the second panel will ask you to specify an empty project or project template. Select project template. You will see a list of Design Templates projects that you have loaded prior as well as various "Baseline Pinout Designs" that contain the pinout and settings for a variety of development kits. If you don't see your design template in the list, click on the link that states install the Design Templates circled below:



Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.


Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.



Prepare the design template in the Quartus Prime software command-line


At the command-line, type the following command:

quartus_sh --platform_install -package <project directory>/<project>.par


Once the process completes, then type:

quartus_sh --platform -name <project>



Note:

* Vendor: Third party from Synaptic Laboratories Ltd.

* ACDS Version: 17.0.0 Standard


Design Details

Device Family

Intel® Cyclone® 10 LP FPGA

Quartus Edition

Intel® Quartus® Prime Standard Edition

Quartus Version

17.0