Intel® MAX® 10 FPGA – Power Management Controller Design Example

Intel® MAX® 10 FPGA – Power Management Controller Design Example

714958
6/2/2016

Introduction

The power management controller design example allows you to allocate some applications in sleep mode during runtime. This reference design includes a simple finite state machine (FSM) to manage low-power state mode by powering down the I/O buffer and GCLK gating during sleep mode. This enables you to turn off portions of the design, thus reducing dynamic power consumption. You can re-enable your application with a fast wake-up time of less than 1 ms. You can modify the reference design based on your application.

Development Kit

Intel® MAX® 10 FPGA Development Kit

Design Details

Device Family

Intel® MAX® 10 FPGAs
Quartus Edition

Intel® Quartus® Prime Standard Edition
Quartus Version

16.0
IP Cores (2)
IP Core IP Core Category
ALTCLKCTRL ClocksPLLsResets
Internal Oscillator ClocksPLLsResets

Detailed Description

Prepare the design template in the Quartus Prime software GUI (version 14.1 and later)


Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.


The second means to bring up the project template is through the New Project Wizard (File -> New Project Wizard). After entering the project name and folder on the first panel, the second panel will ask you to specify an empty project or project template. Select project template. You will see a list of Design Templates projects that you have loaded prior as well as various "Baseline Pinout Designs" that contain the pinout and settings for a variety of development kits. If you don't see your design template in the list, click on the link that states install the Design Templates circled below:



Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.


Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.



Prepare the design template in the Quartus Prime software command-line


At the command-line, type the following command:

quartus_sh --platform_install -package <project directory>/<project>.par


Once the process completes, then type:

quartus_sh --platform -name <project>


Development Kit

Intel® MAX® 10 FPGA Development Kit

Design Details

Device Family

Intel® MAX® 10 FPGAs
Quartus Edition

Intel® Quartus® Prime Standard Edition
Quartus Version

16.0