Intel® Cyclone® 10 LP FPGA – Multiprocessor Nios® II Processor System Reference Design

Intel® Cyclone® 10 LP FPGA – Multiprocessor Nios® II Processor System Reference Design

714850
8/17/2017

Introduction

This reference design demonstrates the features of the Nios® II processor and Qsys system integration tool that are useful for creating systems with multiple processors. This design uses Qsys to build a multiprocessor system containing four processors. Each processor is in a subsystem, creating a hierarchy with four subsystems with a shared memory map, coordinated with pipeline bridges. This system demonstrates a solution for the classic Dining Philosophers' Problem and shows how to use the Nios II Software Build Tools (SBT) to create, build, download, and view stdio output in a console for four applications using shell scripts.

Development Kit

Intel® Cyclone® 10 LP FPGA Evaluation Kit

Design Details

Device Family

Intel® Cyclone® 10 LP FPGA
Quartus Edition

Intel® Quartus® Prime Standard Edition
Quartus Version

17.0
IP Cores (22)
IP Core IP Core Category
Nios II Gen2 Processor NiosII
Nios II Gen2 Processor Unit NiosII
IRQ Mapper QsysInterconnect
JTAG UART ConfigurationProgramming
MM Interconnect QsysInterconnect
Avalon-ST Adapter QsysInterconnect
Avalon-ST Error Adapter QsysInterconnect
Memory-Mapped Demultiplexer QsysInterconnect
Memory-Mapped Multiplexer QsysInterconnect
Avalon-MM Master Agent QsysInterconnect
Avalon-MM Master Translator QsysInterconnect
Avalon-MM Slave Agent QsysInterconnect
Avalon-ST Single Clock FIFO QsysInterconnect
Avalon-MM Slave Translator QsysInterconnect
Memory-Mapped Traffic Limiter QsysInterconnect
Memory-Mapped Router QsysInterconnect
On-Chip Memory (RAM or ROM) OnChipMemory
Altera Avalon Mutex QsysInterconnect
Avalon-MM Pipeline Bridge QsysInterconnect
Reset Controller QsysInterconnect
Interval Timer Peripherals
System ID Peripheral Other

Detailed Description

Prepare the design template in the Quartus Prime software GUI (version 14.1 and later)


Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.


The second means to bring up the project template is through the New Project Wizard (File -> New Project Wizard). After entering the project name and folder on the first panel, the second panel will ask you to specify an empty project or project template. Select project template. You will see a list of Design Templates projects that you have loaded prior as well as various "Baseline Pinout Designs" that contain the pinout and settings for a variety of development kits. If you don't see your design template in the list, click on the link that states install the Design Templates circled below:



Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.


Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.



Prepare the design template in the Quartus Prime software command-line


At the command-line, type the following command:

quartus_sh --platform_install -package <project directory>/<project>.par


Once the process completes, then type:

quartus_sh --platform -name <project>



Note:

* ACDS Version: 17.0.0 Standard


Development Kit

Intel® Cyclone® 10 LP FPGA Evaluation Kit

Design Details

Device Family

Intel® Cyclone® 10 LP FPGA
Quartus Edition

Intel® Quartus® Prime Standard Edition
Quartus Version

17.0