MAX 10 - ADC with Threshold Violation Detection



ADC compares output data with defined threshold data, which can be used as status flag or triggering other circuits when exceed maximum threshold level or when it goes below minimum threshold level.
IP Cores (46)
IP Core IP Core Category
Altera Modular ADC core ADC
Altera Trace ADC Monitor ADC
Altera Trace ADC Monitor Core ADC
Altera Trace ADC Monitor Width Adapter ADC
Reset Controller QsysInterconnect
altera_trace_monitor_endpoint QsysInterconnect
Avalon-ST Adapter QsysInterconnect
Avalon-ST Data Format Adapter QsysInterconnect
Avalon-ST Timing Adapter QsysInterconnect
Altera Modular ADC Control core ADC
Altera Modular ADC Sample Storage core ADC
Altera Modular ADC Sequencer core ADC
Avalon-ST Splitter QsysInterconnect
Altera Modular ADC Threshold Detect core ADC
JTAG Debug Link (internal module) ConfigurationProgramming
Avalon-ST Bytes to Packets Converter QsysInterconnect
Avalon-ST Single Clock FIFO QsysInterconnect
Avalon-ST JTAG Interface QsysInterconnect
Avalon-ST Packets to Bytes Converter QsysInterconnect
Avalon ST Debug Fabric QsysInterconnect
Avalon-ST Demultiplexer QsysInterconnect
Avalon-ST Dual Clock FIFO QsysInterconnect
Avalon-ST Channel Adapter QsysInterconnect
Altera Management Reset Block Other
Avalon-ST Multiplexer QsysInterconnect
Trace Fabric QsysInterconnect
Avalon-MM Pipeline Bridge QsysInterconnect
altera_trace_capture_controller QsysInterconnect
Avalon-ST Pipeline Stage QsysInterconnect
On-Chip Memory (RAM or ROM) OnChipMemory
MM Interconnect QsysInterconnect
Avalon-ST Error Adapter QsysInterconnect
Avalon-MM Slave Agent QsysInterconnect
Avalon-MM Slave Translator QsysInterconnect
Memory-Mapped Demultiplexer QsysInterconnect
Memory-Mapped Multiplexer QsysInterconnect
Memory-Mapped Router QsysInterconnect
Avalon-MM Master Agent QsysInterconnect
Memory-Mapped Traffic Limiter QsysInterconnect
Avalon-MM Master Translator QsysInterconnect
Trace ROM QsysInterconnect
Timestamp monitor QsysInterconnect
transacto_lite SimulationDebugVerification
altera_jtag_avalon_master QsysInterconnect
Avalon Packets to Transaction Converter QsysInterconnect
Avalon ALTPLL ClocksPLLsResets

Detailed Description

Prepare the design template in the Quartus Prime software GUI (version 14.1 and later)

Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.

The second means to bring up the project template is through the New Project Wizard (File -> New Project Wizard). After entering the project name and folder on the first panel, the second panel will ask you to specify an empty project or project template. Select project template. You will see a list of Design Templates projects that you have loaded prior as well as various "Baseline Pinout Designs" that contain the pinout and settings for a variety of development kits. If you don't see your design template in the list, click on the link that states install the Design Templates circled below:

Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.

Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.

Prepare the design template in the Quartus Prime software command-line

At the command-line, type the following command:

quartus_sh --platform_install -package <project directory>/<project>.par

Once the process completes, then type:

quartus_sh --platform -name <project>


* ACDS Version: 16.0.0 Standard

Design Details

Device Family

Intel® MAX® 10 FPGAs

Quartus Edition

Intel® Quartus® Prime Standard Edition

Quartus Version