Cyclone® V FPGA – Logic Solver Design Example

Cyclone® V FPGA – Logic Solver Design Example

714797
4/2/2019

Introduction

Program a "Logic Solver" game on Intel's DE0-CV Development Board! There are 10 challenges programmed into the board. It is your job to decide what the logic function of each challenge is by flipping the input switches and observing the output LEDs. A switch that is flipped "up" is a 1, and a switch flipped "down" is a 0. Likewise, an LED that is on is a 1 while when the LED is off is a 0. The number on the left indicates whether the function is two inputs (2In, using only the two rightmost switches) or three inputs (3In, using the three rightmost switches). You can flip between the different challenges using the buttons on the board: to advance to the next challenge press the rightmost button, or to return to the previous challenge press the button to the left.

Development Kit

Development Kit

Design Details

Device Family

Cyclone® V FPGAs and SoC FPGAs
Quartus Edition

Intel® Quartus® Prime Standard Edition
Quartus Version

18.1
Other Tags

Terasic* DE0-CV Development Board
IP Cores (0)

Detailed Description

Prepare the design template in the Quartus Prime software GUI (version 14.1 and later)


Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.


The second means to bring up the project template is through the New Project Wizard (File -> New Project Wizard). After entering the project name and folder on the first panel, the second panel will ask you to specify an empty project or project template. Select project template. You will see a list of Design Templates projects that you have loaded prior as well as various "Baseline Pinout Designs" that contain the pinout and settings for a variety of development kits. If you don't see your design template in the list, click on the link that states install the Design Templates circled below:



Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.


Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.



Prepare the design template in the Quartus Prime software command-line


At the command-line, type the following command:

quartus_sh --platform_install -package <project directory>/<project>.par


Once the process completes, then type:

quartus_sh --platform -name <project>



Note:

* ACDS Version: 18.1.0 Standard


Development Kit

Development Kit

Design Details

Device Family

Cyclone® V FPGAs and SoC FPGAs
Quartus Edition

Intel® Quartus® Prime Standard Edition
Quartus Version

18.1
Other Tags

Terasic* DE0-CV Development Board