Intel® MAX® 10 FPGA – I/O Module on Intel MAX 10 FPGAs for OPC UA Design Example

Intel® MAX® 10 FPGA – I/O Module on Intel MAX 10 FPGAs for OPC UA Design Example

714783
10/4/2021

Introduction

This is an example of a low-cost I/O module that can be part of an industrial network using Open Platform Communications (OPC) Unified Architecture (UA) communication over Ethernet.

Design Details

Device Family

Intel® MAX® 10 FPGAs

Quartus Edition

Intel® Quartus® Prime Standard Edition

Quartus Version

17.0

IP Cores (0)

Detailed Description

The example demonstrates that is possible to add small devices such as Intel MAX 10 FPGA to an industrial network to perform basic but necessary tasks like IO supervision and monitoring
The example uses the versatility of FPGA to implement different hardware modules such as Triple Speed Ethernet controller, digital inputs, digital outputs, and the NIOS II soft processor. All this hardware is implemented in the FPGA fabric allowing rapid prototyping and application of changes in the field.
Open-source software is also of big importance in this example design. It takes advantage of FreeRTOS, a wide known Real-time Operating System to manage the task execution and scheduling, making the application scalable, reliable, and deterministic.
The TCP/IP services required to connect the device to a LAN are provided in this example by a lightweight version of TCP/IP stack known as lwIP, compatible with FreeRTOS.
Finally, the high-level user application, either OPC UA Client-Server or OPC UA PubSub is implemented using open62541 in "amalgamation" mode, also compatible with FreeRTOS and lwIP.



Prepare the design template in the Quartus Prime software GUI (version 14.1 and later)


Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.


The second means to bring up the project template is through the New Project Wizard (File -> New Project Wizard). After entering the project name and folder on the first panel, the second panel will ask you to specify an empty project or project template. Select project template. You will see a list of Design Templates projects that you have loaded prior as well as various "Baseline Pinout Designs" that contain the pinout and settings for a variety of development kits. If you don't see your design template in the list, click on the link that states install the Design Templates circled below:



Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.


Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.



Prepare the design template in the Quartus Prime software command-line


At the command-line, type the following command:

quartus_sh --platform_install -package <project directory>/<project>.par


Once the process completes, then type:

quartus_sh --platform -name <project>



Note:

* ACDS Version: 17.0std.2 Standard


Design Details

Device Family

Intel® MAX® 10 FPGAs

Quartus Edition

Intel® Quartus® Prime Standard Edition

Quartus Version

17.0