Intel® Cyclone® 10 GX FPGA – Dynamic Reconfiguration with ATX PLL Switching Reference Design

Intel® Cyclone® 10 GX FPGA – Dynamic Reconfiguration with ATX PLL Switching Reference Design

714672
12/14/2017

Introduction

This design example demonstrates the implementation of Intel® Cyclone® 10 GX FPGA Native PHY auxiliary transmit (ATX) phase-locked loop (PLL) switching, channel reconfiguration with an embedded streamer, and recalibration. The two ATX PLLs are used to support two different data rates which could not be achieved with a TX local divider. This design example aims to assist users with the Intel Cyclone 10 GX FPGA transceiver dynamic reconfiguration. The design starts with the transceiver channel running at a 2 Gbps data rate and then reconfigured to 1.5 Gbps using ATX PLL switching and channel reconfiguration. After reconfiguration is complete, a channel recalibration followed by a reset is performed. Incremental data is sent from the TX and loopback to the RX for monitoring. In-System Sources and Probes (ISSP) is used to provide real-time control to the transceiver while the Signal Tap Logic Analyzer is used for status and data monitoring. The dynamic reconfiguration and recalibration commands are performed thro

Development Kit

Intel® Cyclone® 10 GX FPGA Development Kit

Design Details

Device Family

Intel® Cyclone® 10 GX FPGA
Quartus Edition

Intel® Quartus® Prime Pro Edition
Quartus Version

17.1
IP Cores (0)

Detailed Description

Prepare the design template in the Quartus Prime software GUI (version 14.1 and later)


Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.


The second means to bring up the project template is through the New Project Wizard (File -> New Project Wizard). After entering the project name and folder on the first panel, the second panel will ask you to specify an empty project or project template. Select project template. You will see a list of Design Templates projects that you have loaded prior as well as various "Baseline Pinout Designs" that contain the pinout and settings for a variety of development kits. If you don't see your design template in the list, click on the link that states install the Design Templates circled below:



Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.


Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.



Prepare the design template in the Quartus Prime software command-line


At the command-line, type the following command:

quartus_sh --platform_install -package <project directory>/<project>.par


Once the process completes, then type:

quartus_sh --platform -name <project>



Note:

* ACDS Version: 17.1.0 Pro


Development Kit

Intel® Cyclone® 10 GX FPGA Development Kit

Design Details

Device Family

Intel® Cyclone® 10 GX FPGA
Quartus Edition

Intel® Quartus® Prime Pro Edition
Quartus Version

17.1