Intel® Cyclone® 10 LP FPGA – Boot from EPCQ (Serial Flash) Design Example

Intel® Cyclone® 10 LP FPGA – Boot from EPCQ (Serial Flash) Design Example

714511
9/1/2017
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Introduction

This simple reference design demonstrates how to boot from the EPCQ memory on the Intel® Cyclone® 10 LP FPGA Evaluation Kit. It is based on Synaptic Laboratories Ltd's HyperBus Memory Controller (HBMC) intellectual property (IP) core and Intel's Serial Flash Controller IP core. The tutorial describes the key aspects of a pre-configured .qsys reference project and the process of generating and compiling the project. The tutorial then describes how to compile the example Nios® II processor source code, download the firmware into the EPCQ memory device, and run the reference design on the development board. This reference design is actively maintained by Synaptic Laboratories Ltd. This reference design can be easily modified for other development boards and other Intel FPGA families. Includes a free trial IP.

Development Kit

Intel® Cyclone® 10 LP FPGA Evaluation Kit

Design Details

Device Family

Intel® Cyclone® 10 LP FPGA
Quartus Edition

Intel® Quartus® Prime Standard Edition
Quartus Version

17.0
IP Cores (0)

Detailed Description

Prepare the design template in the Quartus Prime software GUI (version 14.1 and later)


Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.


The second means to bring up the project template is through the New Project Wizard (File -> New Project Wizard). After entering the project name and folder on the first panel, the second panel will ask you to specify an empty project or project template. Select project template. You will see a list of Design Templates projects that you have loaded prior as well as various "Baseline Pinout Designs" that contain the pinout and settings for a variety of development kits. If you don't see your design template in the list, click on the link that states install the Design Templates circled below:



Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.


Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.



Prepare the design template in the Quartus Prime software command-line


At the command-line, type the following command:

quartus_sh --platform_install -package <project directory>/<project>.par


Once the process completes, then type:

quartus_sh --platform -name <project>



Note:

* Vendor: Third party from Synaptic Laboratories Ltd.

* ACDS Version: 17.0.0 Standard


Development Kit

Intel® Cyclone® 10 LP FPGA Evaluation Kit

Design Details

Device Family

Intel® Cyclone® 10 LP FPGA
Quartus Edition

Intel® Quartus® Prime Standard Edition
Quartus Version

17.0