Introduction to SDC on RTL and Early Timing Analysis

Description

Timing analysis is a critical aspect of the FPGA design cycle and accurate constrained designs ensure that timing requirements are met. The SDC-on-RTL feature is available as part of the Intel Quartus Prime Pro software which allows you to apply constraints directly on the hierarchical pins defined in your RTL design. In this video I will go over the basics of SDC-on-RTL and the benefits of including it in your new designs.