Transceiver PHY IP Core User Guide

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Arria® V FPGAs and SoC FPGAs Support Arria® V FPGAs and SoC FPGAs Support Cyclone® V FPGAs and SoC FPGAs Support

654670
2012-06-02
Public

Description

Native transceiver PHY for Stratix® V, Arria® V, Arria® V GZ, Cyclone® V, and protocol-specific xcvrs for 10GBASE-R, 10GBASE-KR, 1G/10GbE, XAUI, Interlaken, PCI Express* PIPE, Custom, Low Latency, and Deterministic Latency transceiver PHYs , Transceiver Reconfiguration Controller, and Reset Controller

Usage instructions