SoC Hardware Overview: the Microprocessor Unit

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Intel® FPGA Training Catalog Cyclone® V FPGAs and SoC FPGAs Support Cyclone® V FPGAs and SoC FPGAs Support Cyclone® V FPGAs and SoC FPGAs Support Cyclone® V FPGAs and SoC FPGAs Support

653125
2021-09-08
Public

Description

In this training you will learn about Hard Processor Subsystem (HPS) in the Cyclone® V, Arria® V, and Arria 10 SoCs. The online training includes information about the MPU subsystem, including the ARM® Cortex™-A9 processor core. Various components of the MPU subsystem such as the processor, co-processors, interrupt controller, and caches will be discussed.

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