Software Design Flow for an Arm*-based Intel® SoC FPGA

Description

This course is intended for low level software and firmware engineers and examines the software design flow required to implement software for an Intel® SoC FPGA with the ARM*-based HPS as an FPGA Component IP. This course discusses the tools and methodology necessary to design and verify your system software. You will gain an understanding of exactly what’s required to implement your software with Intel SoC FPGAs.