Debugging with Signal Tap for Intel® FPGAs Office Hours

Description

This training is a recording of the “Debugging with Signal Tap in Intel FPGAs Office Hours” session held on 1/28/2021. Office Hours give you the opportunity to ask questions directly to an Intel FPGA expert and learn from others’ questions. In this Office Hours session, Intel FPGA Training Engineer Steven Strell answers questions about the implementation and use of the Signal Tap embedded logic analyzer debugging tool found in the Intel Quartus® Prime software.